Novel Fabrication Technology for High Yield Sub-100-nm-Gate InP-Based HEMTs

A novel fabrication technology for lateral scale-down of sub-100-nm-gate InP-based HEMTs is presented. The fabricated device, whose structure features a reduced distance between the gate and ohmic metals of less than 100 nm, exhibits low ohmic resistances and improved DC and RF characteristics with good uniformity across a wafer. A fabricated 130-nm-gate lattice-matched InAlAs/InGaAs HEMT exhibits an extrinsic transconductance of 1.3 S/mm. This is 25% increase compared to that of a HEMT fabricated with our conventional process, which is explained by the reduction of R S . The average current-gain-cutoff-frequency (f T ) of 261 GHz was obtained with a small deviation of 9.0 GHz. Uniform characteristics with high yield were also confirmed for HEMTs with shorter gates. The average f T of 290 GHz with a standard deviation of 9.3 GHz was obtained for 55-nm-gate HEMTs. The developed fabrication technology is promising for improving the electrical characteristics of sub-100-nm-gate InP-based HEMTs and for their integration.