A CMOS transistor-only 8-b 4.5-Ms/s pipelined analog-to-digital converter using fully-differential current-mode circuit techniques

Fully-differential current-mode circuit techniques are developed for the design of a pipelined current-mode analog-to-digital converter (IADC) in the standard CMOS digital processes. In the proposed IADC, the 1-b-per-stage architecture based on the reference nonrestoring algorithm is adopted. Thus large component ratios can be avoided and the linearity errors caused by device mismatches can be minimized. As one of the key subcircuits in the IADC, an offset-canceled high speed differential current comparator (CCMP) is proposed and analyzed. In the CCMP, the subtractions of offsets are performed in the current domain without floating capacitors. Moreover, the other key subcircuit, the current sample-and-hold amplifier (CSHA), is also developed to realize the pipeline architecture. An experimental chip for the proposed IADC has been fabricated in 0.8-/spl mu/m n-well CMOS technology. Using a single 5-V power supply, the fabricated IADC can be operated at 4.5-Ms/s conversion rate with a signal-to-noise-and-distortion-ratio (SNDR) of 51 db (effective 8.2-b) for the input signal at 453 kHz. For 8-b resolution, the fabricated IADC can be operated at 4.5-Ms/s conversion rate with both differential nonlinearity (DNL) and integral nonlinearity (INL) below +/-0.6 LSB. The power consumption and the active chip area are 16 mW/b and 0.73 mm/sup 2//b, respectively. >

[1]  S. H. Lewis,et al.  A pipelined 5-Msample/s 9-bit analog-to-digital converter , 1987 .

[2]  Zhenhua Wang.  Current-mode CMOS integrated circuits for analog computation and signal processing: A tutorial , 1991 .

[3]  David J. Allstot,et al.  Fully balanced CMOS current-mode circuits , 1993 .

[4]  W. Guggenbuhl,et al.  On charge injection in analog MOS switches and dummy switch compensation techniques , 1990 .

[5]  C. Mangelsdorf,et al.  A wideband 10-bit, 20 Msps pipelined ADC using current-mode signals , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[6]  John B. Hughes,et al.  Switched-current signal processing for video frequencies and beyond , 1993 .

[7]  John B. Hughes,et al.  Switched-currents : an analogue technique for digital technology , 1993 .

[8]  Charles G. Sodini,et al.  A high-speed CMOS comparator for use in an ADC , 1988 .

[9]  David J. Allstot,et al.  Low-voltage fully-differential CMOS switched-current filters , 1993 .

[10]  Tsuneo Tsukahara,et al.  An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H , 1989 .

[11]  P. Gray,et al.  All-MOS charge redistribution analog-to-digital conversion techniques. I , 1975, IEEE Journal of Solid-State Circuits.

[12]  David J. Allstot,et al.  Switched-current circuit design issues , 1991 .

[13]  Bang-Sup Song,et al.  A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter , 1988 .

[14]  K. Hirata,et al.  A 10 b 50 MHz pipelined CMOS A/D converter with S/H , 1993 .

[15]  D. G. Nairn,et al.  Current mode analog-to-digital converters , 1989, IEEE International Symposium on Circuits and Systems,.

[16]  M. Degrauwe,et al.  A Micropower CMOS-Instrumentation Amplifier , 1985, IEEE Journal of Solid-State Circuits.

[17]  D.A. Hodges,et al.  All-MOS charge-redistribution analog-to-digital conversion techniques. II , 1975, IEEE Journal of Solid-State Circuits.

[18]  Chung-Yu Wu,et al.  A 0.5 mu A offset-free current comparator for high precision current-mode signal processing , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[19]  L. Letham,et al.  A high-performance CMOS 70-MHz palette/DAC , 1987 .

[20]  Stephen H. Lewis,et al.  A 10-b 20-Msample/s analog-to-digital converter , 1992 .

[21]  Masao Nakaya,et al.  An 8-bit high-speed CMOS A/D converter , 1986 .

[22]  D. G. Nairn,et al.  A ratio-independent algorithmic analog-to-digital converter combining current mode and dynamic techniques , 1990 .

[23]  S. J. Daubert,et al.  A transistor-only current-mode Sigma Delta modulator , 1992 .

[24]  M. F. Tompsett,et al.  A 10-b 15-MHz CMOS recycling two-step A/D converter , 1990 .

[25]  D. G. Nairn,et al.  Current-mode algorithmic analog-to-digital converters , 1990 .

[26]  Chung-Yu Wu,et al.  Precise CMOS current sample/hold circuits using differential clock feedthrough attenuation techniques , 1995 .

[27]  Behzad Razavi,et al.  Design techniques for high-speed, high-resolution comparators , 1992 .