Dynamic voltage and frequency scaling for neuromorphic many-core systems

We present a dynamic voltage and frequency scaling technique within SoCs for per-core power management: the architecture allows for individual, self triggered performance-level scaling of the processing elements (PEs) within less than 100ns. This technique enables each core to adjust its local supply voltage and frequency depending on its current computational load. A test chip has been implemented in 28nm CMOS technology, as prototype of the SpiNNaker2 neuromorphic many core system, containing 4 PEs which are operational within the range of 1.1V down to 0.7V at frequencies from 666MHz down to 100MHz; the effectiveness of the power management technique is demonstrated using a standard benchmark from the application domain. The particular domain area of this application specific processor is real-time neuromorphics. Using a standard benchmark — the synfire chain — we show that the total power consumption can be reduced by 45%, with 85% baseline power reduction and a 30% reduction of energy per neuron and synapse computation, all while maintaining biological real-time operation.

[1]  Moshe Abeles,et al.  Synfire chains , 2009, Scholarpedia.

[2]  Gerhard Fettweis,et al.  A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates , 2012, 2012 IEEE International Solid-State Circuits Conference.

[3]  René Schüffny,et al.  A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  Gerhard Fettweis,et al.  10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[5]  J. Stuart PROCEEDINGS - PART II , 1993 .

[6]  Steve B. Furber,et al.  SpiNNaker: Enhanced multicast routing , 2015, Parallel Comput..

[7]  Anders Lansner,et al.  Reducing the computational footprint for real-time BCPNN learning , 2015, Front. Neurosci..

[8]  René Schüffny,et al.  A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits , 2014, IEEE Transactions on Biomedical Circuits and Systems.

[9]  Ad Aertsen,et al.  Functional consequences of correlated excitatory and inhibitory conductances in cortical networks , 2010, Journal of Computational Neuroscience.

[10]  René Schüffny,et al.  A power management architecture for fast per-core DVFS in heterogeneous MPSoCs , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[11]  Jim D. Garside,et al.  SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation , 2013, IEEE Journal of Solid-State Circuits.

[12]  G. Buzsáki,et al.  The log-dynamic brain: how skewed distributions affect network operations , 2014, Nature Reviews Neuroscience.

[13]  Giacomo Indiveri,et al.  A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity , 2006, IEEE Transactions on Neural Networks.

[14]  Bernard Brezzo,et al.  TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Steve B. Furber,et al.  Power analysis of large-scale, real-time neural networks on SpiNNaker , 2013, The 2013 International Joint Conference on Neural Networks (IJCNN).