Propositional approximations for bounded model checking of partial circuit designs

Bounded model checking of partial circuit designs enables the detection of errors even when the implementation of the design is not finished. The behavior of the missing parts can be modeled by a conservative extension of propositional logic, called 01X-logic. Then the transitions of the underlying (incomplete) sequential circuit under verification have to be represented adequately. In this work, we investigate the difference between a relation-oriented and a function-oriented approach for this issue. Experimental results on a large set of examples show that the function-oriented representation is most often superior w. r. t. (1) CPU runtime and (2) accuracy regarding the ability to find a counterexample, such that by using the function-oriented approach an increase of accuracy up to 210% and a speed-up of the CPU runtime up to 390% compared to the relation-oriented approach are achieved. But there are also relevant examples, e. g. a VLIW-ALU, for which the relation-oriented approach outperforms the function-oriented one by 300% in terms of CPU-time, showing that both approaches are efficient for different scenarios.

[1]  Bernd Becker,et al.  Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs , 2006, Seventh International Workshop on Microprocessor Test and Verification (MTV'06).

[2]  Armin Biere,et al.  Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking , 2000, CAV.

[3]  Randal E. Bryant,et al.  Formal verification by symbolic evaluation of partially-ordered trajectories , 1995, Formal Methods Syst. Des..

[4]  Bernd Becker,et al.  Computation of minimal counterexamples by using black box techniques and symbolic methods , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[5]  In-Cheol Park,et al.  SAT-based unbounded symbolic model checking , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[6]  Robert K. Brayton,et al.  DAG-aware AIG rewriting: a fresh look at combinational logic synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[7]  Thomas Filkorn.  Functional Extension of Symbolic Model Checking , 1991, CAV.

[8]  Edmund M. Clarke,et al.  Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..

[9]  Christoph Scholl,et al.  Approximate Symbolic Model Checking for Incomplete Designs , 2004, FMCAD.

[10]  Andreas Kuehlmann.  Dynamic transition relation simplification for bounded property checking , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[11]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[12]  Koen Claessen,et al.  A New SAT-Based Algorithm for Symbolic Trajectory Evaluation , 2005, CHARME.

[13]  Carl-Johan H. Seger,et al.  An industrially effective environment for formal hardware verification , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Edmund M. Clarke,et al.  Model Checking , 1999, Handbook of Automated Reasoning.

[15]  Bernd Becker,et al.  On Combining 01X-Logic and QBF , 2007, EUROCAST.

[16]  Malay K. Ganai,et al.  Robust Boolean reasoning for equivalence checking and functional property verification , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Tiziano Villa,et al.  VIS: A System for Verification and Synthesis , 1996, CAV.

[18]  Bernd Becker,et al.  On SAT-based Bounded Invariant Checking of Blackbox Designs , 2005, 2005 Sixth International Workshop on Microprocessor Test and Verification.

[19]  Masahiro Fujita,et al.  Symbolic model checking using SAT procedures instead of BDDs , 1999, DAC '99.

[20]  Aarti Gupta,et al.  Efficient SAT-based unbounded symbolic model checking using circuit cofactoring , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[21]  Ofer Strichman,et al.  Bounded model checking , 2003, Adv. Comput..

[22]  Michael S. Hsiao,et al.  Testing, verification, and diagnosis in the presence of unknowns , 2000, Proceedings 18th IEEE VLSI Test Symposium.