On Software Simulation for MPSoC

The performance estimation of applications running on Multi-Processor System-On-Chip (MPSoC) is required to perform software and hardware design choices and design validations. As cycle accurate simulation is very time consuming, and may have a level of accuracy that is not always needed, simulation at higher levels of abstraction is recognized as a way to perform early validation of software. Although even very abstract executable models provide interesting functional validation capabilities, they quickly become unsuitable when timing becomes an issue.

[1]  Frank Ghenassia.  Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems , 2010 .

[2]  Stefan Heinen,et al.  Using a dataflow abstracted virtual prototype for HdS-design , 2009, 2009 Asia and South Pacific Design Automation Conference.

[3]  Guy Bois,et al.  SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS , 2003, FDL.

[4]  Alan D. George,et al.  RapidIO for radar processing in advanced space systems , 2007, TECS.

[5]  Daniel Gajski,et al.  Top-down system level design methodology using SpecC, VCC and SystemC , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[6]  Jean Paul Calvez,et al.  Uninterpreted co-simulation for performance evaluation of Hw/Sw systems , 1996, Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96.

[7]  Frédéric Pétrot,et al.  Efficient combinational loops handling for cycle precise simulation of system on a chip , 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).

[8]  Florence Maraninchi,et al.  A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip , 2008, 2008 Design, Automation and Test in Europe.

[9]  Alberto L. Sangiovanni-Vincentelli,et al.  A compilation-based software estimation scheme for hardware/software co-simulation , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).

[10]  Frédéric Pétrot,et al.  Using binary translation in event driven simulation for fast and flexible MPSoC simulation , 2009, CODES+ISSS '09.

[11]  Fabrice Bellard,et al.  QEMU, a Fast and Portable Dynamic Translator , 2005, USENIX ATC, FREENIX Track.

[12]  Eric Cheung,et al.  Fast and accurate performance simulation of embedded software for MPSoC , 2009, 2009 Asia and South Pacific Design Automation Conference.

[13]  Ahmed Amine Jerraya,et al.  Platform-based software design flow for heterogeneous MPSoC , 2008, TECS.

[14]  Ahmed Amine Jerraya,et al.  Timed HW-SW cosimulation using native execution of OS and application SW , 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..

[15]  Jong-Yeol Lee,et al.  Timed compiled-code simulation of embedded software for performance analysis of SOC design , 2002, DAC '02.

[16]  Michael F. P. O'Boyle,et al.  DATE '08 Proceedings of the conference on Design, automation and test in Europe , 2008 .

[17]  Luca Benini,et al.  SystemC Cosimulation and Emulation of Multiprocessor SoC Designs , 2003, Computer.

[18]  Andreas Gerstlauer,et al.  Retargetable profiling for rapid, early system-level design space exploration , 2004, Proceedings. 41st Design Automation Conference, 2004..

[19]  Ahmed Amine Jerraya,et al.  Building fast and accurate SW simulation models based on hardware abstraction layer and simulation environment abstraction layer , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[20]  Pascal Sainrat,et al.  A Context-Parameterized Model for Static Analysis of Execution Times , 2009, Trans. High Perform. Embed. Archit. Compil..

[21]  Donald E. Thomas,et al.  High level cache simulation for heterogeneous multiprocessors , 2004, Proceedings. 41st Design Automation Conference, 2004..

[22]  Kingshuk Karuri,et al.  A SW performance estimation framework for early system-level-design using fine-grained instrumentation , 2006, Proceedings of the Design Automation & Test in Europe Conference.