Zero-aliasing space compression using a single periodic output and its application to testing of embedded cores

A structure-independent method for space compaction based on a new generic scheme is presented in this paper. The compactor compresses test responses of a circuit-under-test (CUT) to a single periodic data stream with guaranteed zero-aliasing, and can be designed only from the knowledge of the test set and the corresponding fault-free responses. An additional response logic and a special code checker are used to design the compactor. The same test set given for the CUT also detects all multiple stuck-at faults in the response logic, and almost all the faults in the rest of the compactor. Further, time compaction is also easily achieved. Since the design does not need any structural information of the CUT, it is useful for testing embedded cores.

[1]  John P. Hayes,et al.  Testing ICs: Getting to the Core of the Problem , 1996, Computer.

[2]  Michael Gössel,et al.  A new totally error propagating compactor for arbitrary cores with digital interfaces , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[3]  John P. Hayes,et al.  High-level test generation using physically-induced faults , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[4]  Michael Gössel,et al.  Self-Checking Comparator with One Periodic Output , 1996, IEEE Trans. Computers.

[5]  John P. Hayes,et al.  Test response compaction using multiplexed parity trees , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Zvi Kohavi,et al.  Detection of Multiple Faults in Combinational Logic Networks , 1972, IEEE Transactions on Computers.

[7]  Michael Gössel,et al.  A structural approach for space compaction for concurrent checking and BIST , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[8]  John P. Hayes,et al.  Optimal Zero-Aliasing Space Compaction of Test Responses , 1998, IEEE Trans. Computers.

[9]  Debashis Bhattacharya Hierarchical test access architecture for embedded cores in an integrated circuit , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[10]  John P. Hayes,et al.  Efficient test response compression for multiple-output circuits , 1994, Proceedings., International Test Conference.

[11]  John P. Hayes,et al.  Test-set preserving logic transformations , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[12]  Nur A. Touba,et al.  Synthesis of zero-aliasing elementary-tree space compactors , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[13]  Yervant Zorian,et al.  Test requirements for embedded core-based systems and IEEE P1500 , 1997, Proceedings International Test Conference 1997.