Core-Based Architecture for Data Transfer Control in SoC Design

The functionality of many digital circuits is strongly dependent on high speed data exchange between data source and sink elements. In order to alleviate the main processor’s work, it is usually interesting to isolate high speed data transfers from all other control tasks. A generic architecture, based on configurable cores, has been achieved for circuits communicating with an external system and with extensive data exchange requirements. Design reuse has been improved by means of a software application that helps in architectural verification and performance analysis tasks. Two applications implemented on FPGA technology are presented to validate the proposed architecture.