Performance Enhancement of MRPSOC for Multimedia Applications

There are several techniques to reconfigure the instruction set processors. One such technique is multi-reconfigurable instruction set processor system on chip (MRPSOC). Integration of MRPSOC and multigrain parallelism is done to improve the performance of SOC. By using MRPSOC, the performance of the system is increased. Multimedia application computing can be accelerated by using multigrain parallelism. By implementing this integrated processor, extra features can be added to MRPSOC. Multiple data is packed in a single register which forms a vector; this vector of multiple data is fetched to MRPSOC at a time. Since MRPSOC is a combination of MPSOC and RISP processor, instruction-level parallelism can be implemented in MRPSOC. After the execution of operations in MRPSOC, the multiple outputs can be stored at different memory locations of same memory system simultaneously. This proposal is aimed to design MRPSOC interfaced with data-level parallelism, instruction-level parallelism, and memory transfer-level parallelism. Form this paper, it is concluded that by using both MRPSOC and multigrain parallelism in common platform, high-speed computation can be achieved for multimedia applications. Proposed design takes 28% less time to complete the task compared to MPSOC. Further completion time will be reduced for tasks having repetitive instructions.

[1]  Sharad Malik,et al.  From ASIC to ASIP: the next design discontinuity , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[2]  Susan J. Eggers,et al.  Improving balanced scheduling with compiler optimizations that increase instruction-level parallelism , 1995, PLDI '95.

[3]  Roberto Guerrieri,et al.  A VLIW processor with reconfigurable instruction set for embedded applications , 2003 .

[4]  I. Kuroda,et al.  Multimedia processors , 1998, Proc. IEEE.

[5]  Ahmed Amine Jerraya,et al.  Multiprocessor System-on-Chip (MPSoC) Technology , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Paolo Ienne,et al.  Exact and approximate algorithms for the extension of embedded processor instruction sets , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Achim Nohl,et al.  Application specific processor design: Architectures, design methods and tools , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[8]  Rudy Lauwereins,et al.  Reconfigurable instruction set processors: a survey , 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).

[9]  Earl E. Swartzlander.  Application Specific Processors , 1997 .

[10]  Xiaoya Fan,et al.  Investigation on Multi-Grain Parallelism in Chip Multiprocessor for Multimedia Application , 2009, 2009 International Conference on Information Engineering and Computer Science.

[11]  Thorsten Grotker,et al.  System Design with SystemC , 2002 .

[12]  Siamak Mohammadi,et al.  A platform for multi reconfigurable instruction set processor system on chip (MRPSoC) , 2013, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013).

[13]  Parvathy Asokan.  A NOVEL MRPSoC PROCESSOR FOR DISPATCH TIME CURTAILMENT , 2014 .

[14]  Xiaoya Fan,et al.  The Integration of Multimedia Process Unit into an Embedded Processor , 2007, 2007 IEEE International Conference on Integration Technology.