High-level synthesis and codesign methods: An application to a Videophone Codec

This paper describes a high-level multi-HDL design process applied to an industrial design of a single chip Videophone Codec. It makes use of many state-of-the-art design tools and methods: Behavioural VHDL control path synthesis for the controller of the Codec motion estimator; behavioural DSP synthesis from Silage to generate an application-specific calculation unit that performs vector prediction for the motion estimator; retargetable C compilation for an embedded application-specific microcontroller and multi-level (behavioural, RTL, gate) and multi-language (VHDL, Silage, C) co-simulation. We show that, with respect to a manual design process, the use of these tools led to the following results: a five-fold reduction in the source HDL description complexity; equal or better timing performance; silicon area within 15% (4% area overhead for the DSP operator, and 14% overhead for the controller) and automatically compiled assembly code (from ANSI C descriptions) that is as compact as hand-coded assembler. We also identified a strong need to pay attention to design verification issues, especially when dealing with multi-level descriptions and multiple languages. Validation of the design was the single most time consuming part of the process.

[1]  Pierre G. Paulin,et al.  Flexware: A flexible firmware development environment for embedded systems , 1994, Code Generation for Embedded Processors.

[2]  Pierre G. Paulin,et al.  Flexible modeling environment for embedded systems design , 1994, Third International Workshop on Hardware/Software Codesign.

[3]  Hugo De Man,et al.  Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms , 1990, Proc. IEEE.

[4]  P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .

[5]  Hong Ding,et al.  VHDL Based Design Methodology for Hierarchy , 1995 .

[6]  T. C. May,et al.  Instruction-set matching and selection for DSP and ASIP code generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[7]  R. Preston Gurd.  Experience developing microcode using a high level language , 1983, SIGM.

[8]  Pierre G. Paulin,et al.  Flexible modeling environment for embedded systems design , 1994, CODES.

[9]  Donatella Sciuto,et al.  A methodology for control-dominated systems codesign , 1994, Third International Workshop on Hardware/Software Codesign.

[10]  Pierre G. Paulin,et al.  DSP design tool requirements for embedded systems: A telecommunications industrial perspective , 1995, J. VLSI Signal Process..

[11]  Hugo De Man,et al.  Synthesis of High Throughput DSP ASICs Using Application Specific Datapaths , 1994 .

[12]  Mohamed Abid,et al.  A unified model for co-simulation and co-synthesis of mixed hardware/software systems , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[13]  Donatella Sciuto,et al.  A methodology for control-dominated systems codesign , 1994, CODES '94.

[14]  Yves Durand,et al.  A single chip videophone video encoder/decoder , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[15]  Hong Ding,et al.  Structured Design Methodology for High-Level Design , 1994, 31st Design Automation Conference.

[16]  Hong Ding,et al.  VHDL based design methodology for hierarchy and component re-use , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[17]  Pierre G. Paulin,et al.  Register assignrnent through resource classification for ASIP microcode generation , 1994, IEEE/ACM International Conference on Computer-Aided Design.