A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS

This paper presents a source synchronous receiver data lane design in 65nm CMOS process. The data lane circuit consists of a pre-amplifier which can compensate over 8dB channel loss and a half-rate digital CDR based on phase-interpolator. The CDR bandwidth is programmable by using a digital FIR filter. This design uses variable offset amplifier technology to increase sensitivity of the receiver. And a common-mode level shift function is implemented in order to increase the bandwidth of the pre-amplifier. The area for one data channel without ESD and PAD is 0.05 mm^2 and power consumption is 35mw for 1.2V supply.

[1]  Bryan Casper,et al.  A 47$\,\times\,$ 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[2]  M. Horowitz,et al.  A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS , 2007, IEEE Journal of Solid-State Circuits.

[3]  James E. Jaussi,et al.  A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS , 2010, ISSCC.

[4]  Behzad Razavi,et al.  Low-Power CMOS Equalizer Design for 20-Gb/s Systems , 2011, IEEE Journal of Solid-State Circuits.

[5]  James E. Jaussi,et al.  A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[6]  Thomas Toifl,et al.  A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[7]  Zhihua Wang,et al.  A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS , 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).