Invited: Approximate computing with partially unreliable dynamic random access memory — Approximate DRAM

In the context of approximate computing, Approximate Dynamic Random Access Memory (ADRAM) enables the tradeoff between energy efficiency, performance and reliability. The inherent error resilience of applications allows sacrificing data storage robustness and stability by lowering the refresh rate or disabling refresh in DRAMs completely. Consequently, it is important to know exactly the statistical DRAM behavior with respect to retention time, process variation and temperature to manage this trade-off and thereby deliberately exploiting the error resilience of different target applications.

[1]  Norbert Wehn,et al.  Exploiting expendable process-margins in DRAMs for run-time performance optimization , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  Chen-Yong Cher,et al.  Understanding soft errors in uncore components , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[3]  Song Liu,et al.  Flikker: saving DRAM refresh-power through critical data partitioning , 2011, ASPLOS XVI.

[4]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[5]  Richard Veras,et al.  RAIDR: Retention-aware intelligent DRAM refresh , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[6]  Arnab Raha,et al.  Quality-aware data allocation in approximate DRAM* , 2015, 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).

[7]  Dan Grossman,et al.  EnerJ: approximate data types for safe and general low-power computation , 2011, PLDI '11.

[8]  Yongjun Park,et al.  An eDRAM-Based Approximate Register File for GPUs , 2016, IEEE Design & Test.

[9]  Onur Mutlu,et al.  AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems , 2015, 2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks.

[10]  Scott A. Mahlke,et al.  Quality Control for Approximate Accelerators by Error Prediction , 2016, IEEE Design & Test.

[11]  J. Lucas,et al.  Sparkk : Quality-Scalable Approximate Storage in DRAM , 2014 .

[12]  Jörg Henkel.  Approximate Computing: Solving Computing's Inefficiency Problem? , 2016, IEEE Des. Test.

[13]  Norbert Wehn,et al.  Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs , 2015, MEMSYS.

[14]  Y.J. Park,et al.  Prediction of data retention time distribution of DRAM by physics-based statistical Simulation , 2005, IEEE Transactions on Electron Devices.

[15]  Kaushik Roy,et al.  Invited — Cross-layer approximations for neuromorphic computing: From devices to circuits and systems , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[16]  Narayanan Vijaykrishnan,et al.  Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems , 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

[17]  David Atienza,et al.  3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[18]  Kinam Kim,et al.  A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs , 2009, IEEE Electron Device Letters.

[19]  Norbert Wehn,et al.  Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[20]  Onur Mutlu,et al.  Adaptive-latency DRAM: Optimizing DRAM timing for the common-case , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

[21]  Norbert Wehn,et al.  Towards variation-aware system-level power estimation of DRAMs: An empirical approach , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[22]  Muhammad Shafique,et al.  Invited: Cross-layer approximate computing: From logic to architectures , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[23]  Onur Mutlu,et al.  Mitigating the Memory Bottleneck With Approximate Load Value Prediction , 2016, IEEE Design & Test.

[24]  Jie Han,et al.  Approximate computing: An emerging paradigm for energy-efficient design , 2013, 2013 18th IEEE European Test Symposium (ETS).

[25]  Michael Engel,et al.  Improving the fault resilience of an H.264 decoder using static analysis methods , 2013, TECS.

[26]  Luca Benini,et al.  Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[27]  Norbert Wehn,et al.  DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework , 2015, IPSJ Trans. Syst. LSI Des. Methodol..

[28]  Onur Mutlu,et al.  An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms , 2013, ISCA.

[29]  Yu Wang,et al.  Exploring the Precision Limitation for RRAM-Based Analog Approximate Computing , 2016, IEEE Design & Test.

[30]  Norbert Wehn,et al.  Efficient reliability management in SoCs - an approximate DRAM perspective , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

[31]  Bruce Jacob,et al.  Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

[32]  Norbert Wehn,et al.  A Cross-Layer Reliability Design Methodology for Efficient, Dependable Wireless Receivers , 2014, ACM Trans. Embed. Comput. Syst..