A novel loop adaptive hardware design for Coarse-Grained Reconfigurable array
暂无分享,去创建一个
[1] Wenjie Wang,et al. A reconfigurable multi-processor SoC for media applications , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[2] Markus Weinhardt,et al. PACT XPP—A Self-Reconfigurable Data Processing Architecture , 2003, The Journal of Supercomputing.
[3] Fadi J. Kurdahi,et al. MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.
[4] Longxing Shi,et al. Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications , 2012, IEICE Trans. Inf. Syst..
[5] Longxing Shi,et al. Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications , 2012, IEICE Trans. Inf. Syst..
[6] Kiyoung Choi. Coarse-Grained Reconfigurable Array: Architecture and Application Mapping , 2011, IPSJ Trans. Syst. LSI Des. Methodol..
[7] Scott A. Mahlke,et al. IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors , 1998, 25 Years ISCA: Retrospectives and Reprints.
[8] Rudy Lauwereins,et al. ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.
[9] Yunheung Paek,et al. Improving performance of nested loops on reconfigurable array processors , 2012, TACO.