Prediction of Gate Dielectric Breakdown in the CDM timescale utilizing very fast transmission line pulsing

In this paper, prediction of Gate Oxide Breakdown (GOB) in the Charged Device Model (CDM) timeframe is performed. The prediction does not require lengthy low-voltage Constant Voltage Stress (CVS) measurements but instead utilizes short (less than 5 seconds per measurement) high-voltage CVS measurements as well as quick Ramped Voltage Stress (RVS) measurements to calculate a voltage to breakdown (VBD) in the CDM timeframe as well as the dispersal of actual TDDBs for each oxide area and thickness. To this end, a modified form of the Power Law, called the Trapezoidal Power Law, is derived to simplify data processing and allow comparisons between RVS and CVS. The prediction methodology using the Trapezoidal Power Law is finally demonstrated to predict the exact voltage required to consistently damage the oxide within a single pulse.

[1]  J. Stathis.  Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits , 2001 .

[2]  Elyse Rosenbaum,et al.  Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[3]  A. Ghetti,et al.  Field acceleration for oxide breakdown-can an accurate anode hole injection model resolve the E vs. 1/E controversy? , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[4]  J. Stathis.  Physical and predictive models of ultra thin oxide reliability in CMOS devices and circuits , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

[5]  Anabela Veloso,et al.  Reliability screening of high-k dielectrics based on voltage ramp stress , 2007, Microelectron. Reliab..

[6]  E. Rosenbaum,et al.  Gate oxide reliability under ESD-like pulse stress , 2004, IEEE Transactions on Electron Devices.

[7]  Alan Mathewson,et al.  Correlation of SiO2 lifetimes from constant and ramped voltage measurements , 1996 .

[8]  Jordi Suñé,et al.  Physics-Based Percolation Model of Oxide Breakdown , 2007 .

[9]  L. G. Henry.  Transmission Line Pulse Testing of the ESD Protection Structures of ICs .-A Failure Analysts Perspective . , 2001 .

[10]  Jordi Suñé,et al.  Power-law voltage acceleration: A key element for ultra-thin gate oxide reliability , 2005, Microelectron. Reliab..

[11]  J. Stathis,et al.  Dielectric breakdown mechanisms in gate oxides , 2005 .

[12]  S. Dimitrijev.  Principles of semiconductor devices , 2005 .

[13]  Yuanzhong Zhou,et al.  Effect of large device capacitance on FICDM peak current , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

[14]  Bonnie E. Weir,et al.  Gate dielectric breakdown in the time-scale of ESD events , 2005, Microelectron. Reliab..

[15]  S. Malobabic,et al.  Gate oxide evaluation under very fast transmission line pulse (VFTLP) CDM-type stress , 2008, 2008 7th International Caribbean Conference on Devices, Circuits and Systems.

[16]  D. J. DiMaria.  Explanation for the oxide thickness dependence of breakdown characteristics of metal-oxide-semiconductor structures , 1997 .

[17]  Melanie Etherton.  Charged Device Model (CDM) ESD in ICs , 2006 .

[18]  A. Bravaix,et al.  Ultra-thin gate oxide reliability in the ESD time domain , 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

[19]  Jordi Suñé,et al.  Trapped charge distributions in thin (10 nm) SiO/sub 2/ films subjected to static and dynamic stresses , 1998 .