A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC

This paper presents design-for-debug (DfD) methods for the reuse of network-on-chip (NoC) as a debug data path in an NoC-based system-on-chip (SoC). We propose on-chip core debug supporting logics which can support transaction-based debug. A debug interface unit is also presented to enable debug data transfer through an NoC between an external debugger and a core-under-debug (CUD). The proposed approach supports debug of designs with multiple clock domains. It also supports collection of trace signatures to facilitate debug of long pattern sequences. Experimental results show that single and multiple stepping through transactions are feasible with moderately low area overhead. We also present simulation result to verify proper operation of the debug components.

[1]  Alexandre M. Amory,et al.  Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism , 2007, IET Comput. Digit. Tech..

[2]  Kees G. W. Goossens,et al.  An event-based monitoring service for networks on chip , 2005, TODE.

[3]  Yervant Zorian,et al.  Wrapper design for embedded core test , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[4]  Sandeep Kumar Goel,et al.  Design for debug: catching design errors in digital chips , 2002, IEEE Design & Test of Computers.

[5]  Jaehoon Song,et al.  Low-Cost Scan Test for IEEE-1500-Based SoC , 2008, IEEE Transactions on Instrumentation and Measurement.

[6]  Fawnizu Azmadi Hussin,et al.  Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints , 2007, 12th IEEE European Test Symposium (ETS'07).

[7]  Ieee Standard Test Access Port and Boundary-scan Architecture Ieee-sa Standards Board , 2001 .

[8]  Giovanni De Micheli,et al.  Design, synthesis, and test of networks on chips , 2005, IEEE Design & Test of Computers.

[9]  Qiang Xu,et al.  A Multi-Core Debug Platform for NoC-Based Systems , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[10]  B. Vermeulen,et al.  Core-based scan architecture for silicon debug , 2002, Proceedings. International Test Conference.

[11]  Kees G. W. Goossens,et al.  Transaction-Based Communication-Centric Debug , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[12]  P. Moore,et al.  Non-Concurrent On-Line Testing Via Scan Chains , 2006, 2006 IEEE Autotestcon.

[13]  Matthias Beck,et al.  Logic design for on-chip test clock generation - implementation details and impact on delay test quality , 2005, Design, Automation and Test in Europe.

[14]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[15]  Tom Waayers,et al.  Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain , 2005, IEEE International Conference on Test, 2005..

[16]  Bart Vermeulen,et al.  IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips , 2002, Proceedings. International Test Conference.

[17]  Derek Feltham,et al.  Full Hold-Scan Systems in Microprocessors: Cost/Benefit Analysis , 2004 .

[18]  Erik Jan Marinissen,et al.  Infrastructure for modular SOC testing , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[19]  Kees G. W. Goossens,et al.  Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective , 2006, 2006 International Symposium on Industrial Embedded Systems.