Fast locking and high accurate current matching phase-locked loop

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PLL circuit is designed based on the 0.35 um 2P4M CMOS process with 3.3 V/5 V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PLL and its charge pump sink and source current mismatch is only 0.008%.

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