Architectures of Delay Line ADC and Delay Cells for Digital DC-DC Converters

A survey and classification of architectures is presented in this paper for delay line ADC and its delay cells targeting digital control of DC-DC converters. Previously presented designs are identified as particular cases of the proposed classification. In order to optimize occupied area and power consumption, a general architecture is designed, which includes one delay line and thermometer-decode. And a particular example of the delay line ADC is described. The ADC operates at 4 MHz switching frequency and has low power consumption and small area. Experimental results verify the functionality of the designed delay line ADC.

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