New in-place strategy for a mixed-radix FFT processor

This paper proposes a fast Fourier transform (FFT) processor using a new in-place strategy and the mixed-radix algorithm. The proposed processor uses only two N-word memories for a continuous flow FFT implementation, due to the new in-place strategy, while existing continuous FFT processors use four N-word memories. In addition, the proposed processor satisfies both small area and real-time processing requirement. The gate count of the processor is 37,000 and the number of clock cycles is 640 for a 512-point FFT. Hence, the proposed FFT processor can reduce the gate count and memory size compared with existing FFT processors.

[1]  Chien-Ming Wu,et al.  Design of an efficient FFT processor for DAB system , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[2]  Chin-Liang Wang,et al.  A novel DHT-based FFT/IFFT processor for ADSL transceivers , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[3]  E. L. Zapata,et al.  Area-efficient architecture for Fast Fourier transform , 1999 .

[4]  D. J. Skellern,et al.  VLSI for OFDM , 1998 .

[5]  Lewis Johnson,et al.  Conflict free memory addressing for dedicated FFT hardware , 1992 .

[6]  Jun Rim Choi,et al.  A 2048 complex point FFT architecture for digital audio broadcasting system , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[7]  Hannu Tenhunen,et al.  A pipelined shared-memory architecture for FFT processors , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).

[8]  Peter Liu,et al.  Minimizing the memory requirement for continuous flow FFT implementation: continuous flow mixed mode FFT (CFMM-FFT) , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).