A post-processing approach to minimize TSV number for high-level synthesis of 3D ICs

3D IC technology stacks multiple integrated chips and its application is more and more popular. Therefore, developing CAD tools for the requirement of 3D architecture becomes urgent and important. In this paper, we present an integer linear programming (ILP) model for the application of resource layer assignment in high level synthesis. Our objective is to minimize the number of signal through-silicon-vias (TSVs) under both the layer number constraint and the footprint area constraint. Our approach has two possible applications: (1) a post-processing method to perform TSV number minimization for high-level synthesis of 3D ICs; (2) a post-processing method to transfer a design from 2D IC structure into 3D IC structure. Note that our approach guarantees minimizing the number of TSVs. Experimental data show that our approach works well in practice.

[1]  Ranga Vemuri,et al.  Simultaneous scheduling, binding and layer assignment for synthesis of vertically integrated 3D systems , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[2]  Shih-Hsu Huang,et al.  An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management , 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[3]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.

[4]  Paul R. Norton,et al.  Vertically integrated sensor arrays: VISA , 2004, SPIE Defense + Commercial Sensing.

[5]  Lei Jiang,et al.  Die Stacking (3D) Microarchitecture , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[6]  K.C. Saraswat,et al.  Thermal analysis of heterogeneous 3D ICs with various integration scenarios , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[7]  Shih-Hsu Huang,et al.  Timing driven power gating in high-level synthesis , 2009, 2009 Asia and South Pacific Design Automation Conference.

[8]  Srinivas Katkoori,et al.  A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[9]  Sheqin Dong,et al.  Simultaneous buffer and interlayer via planning for 3D floorplanning , 2009, 2009 10th International Symposium on Quality Electronic Design.

[10]  Ranga Vemuri,et al.  On physical-aware synthesis of vertically integrated 3D systems , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[11]  Sung Kyu Lim,et al.  Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs , 2009, SLIP '09.