Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem

This paper presents an area and power-efficient variable-size DCT architecture for HEVC application. We develop a reconfigurable and scalable shift-and-add unit (SAU) embedded in our 1D-DCT architecture by leveraging Muxed-MCM problem with the aim of increasing the hardware reusability in the arithmetic units, while reducing the hardware cost. The key idea behind the proposed architecture is the fact that in most of the times (≈90%) the lower point DCTs are performed when the higher point SAUs remain unused. Accordingly, we focus on merging the SAUs of lower point DCTs into the higher point DCTs to compute multiple lower point DCTs in parallel as well as processing any combination of transform sizes. The experimental results show that the proposed folded and fully-parallel 2D-DCT architectures achieve the best hardware cost by 45% and 30% reduction in gate count, respectively, amongst the existing architectures. Moreover, power saving of 55% and 32% can be achieved for the proposed folded and fully-parallel architectures, respectively, where they can process 60 fps of 4K and 30 fps of 8K UHD video sequences in 300 MHz operating frequency.

[1]  Keshab K. Parhi,et al.  VLSI digital signal processing systems , 1999 .

[2]  Takao Onoye,et al.  High-performance multiplierless transform architecture for HEVC , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[3]  Chuohao Yeo,et al.  Efficient Integer DCT Architectures for HEVC , 2014, IEEE Transactions on Circuits and Systems for Video Technology.

[4]  Weiwei Shen,et al.  A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards , 2012, 2012 IEEE International Conference on Multimedia and Expo.

[5]  James C. Hoe,et al.  Time-Multiplexed Multiple-Constant Multiplication , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Kishor Sarawadekar,et al.  WHT and Matrix Decomposition-Based Approximated IDCT Architecture for HEVC , 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Ilker Hamzaoglu,et al.  A computation and energy reduction technique for HEVC Discrete Cosine Transform , 2016, IEEE Transactions on Consumer Electronics.

[8]  Ayman Alfalou,et al.  A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Madhukar Budagavi,et al.  Core Transform Design in the High Efficiency Video Coding (HEVC) Standard , 2013, IEEE Journal of Selected Topics in Signal Processing.

[10]  Bruno Zatt,et al.  An HEVC multi-size DCT hardware with constant throughput and supporting heterogeneous CUs , 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

[11]  Muhammad Usman Shahid,et al.  Point DCT VLSI Architecture for Emerging HEVC Standard , 2012, VLSI Design.

[12]  Somayeh Timarchi,et al.  Low-power DCT-based compressor for wireless capsule endoscopy , 2017, Signal Process. Image Commun..

[13]  Guido Masera,et al.  Adaptive Approximated DCT Architectures for HEVC , 2017, IEEE Transactions on Circuits and Systems for Video Technology.

[14]  Guido Masera,et al.  An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding , 2020, IEEE Transactions on Circuits and Systems for Video Technology.

[15]  Wai-kuen Cham,et al.  Recursive Integer Cosine Transform for HEVC and Future Video Coding Standards , 2017, IEEE Transactions on Circuits and Systems for Video Technology.

[16]  Indrajit Chakrabarti,et al.  A Novel Algorithmic Approach for Efficient Realization of 2-D-DCT Architecture for HEVC , 2019, IEEE Transactions on Consumer Electronics.

[17]  Seongsoo Lee,et al.  2-D Large Inverse Transform (16×16, 32×32) for HEVC (High Efficiency Video Coding) , 2012 .

[18]  Chih-Peng Fan,et al.  A Fast Algorithm-Based Cost-Effective and Hardware-Efficient Unified Architecture Design of 4 × 4, 8 × 8, 16 × 16, and 32 × 32 Inverse Core Transforms for HEVC , 2016, J. Signal Process. Syst..

[19]  Masahiro Fujita,et al.  Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme , 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

[20]  Sang Yoon Park,et al.  Flexible integer DCT architectures for HEVC , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[21]  Kishor Sarawadekar,et al.  Approximated Core Transform Architectures for HEVC Using WHT-Based Decomposition Method , 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  Somayeh Timarchi,et al.  Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix , 2019, Microelectron. J..

[23]  Kishor Sarawadekar,et al.  An Optimized Architecture of HEVC Core Transform Using Real-Valued DCT Coefficients , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.