A novel critical path heuristic for fast fault grading

A novel fault grading heuristic is presented, based on the critical path tracing technique that tackles the problems associated with fan-out reconverging nodes (FORNs) without using forward propagation of the fault effects. To determine the criticality status of a fan-out reconverging node, which can differ from that of its fan-out branches (FOBs), the concepts of evidencing and masking paths are used. Using the statistics from exact fault simulations, heuristic rules are derived for the generation of masking and evidencing paths. The results obtained on benchmark circuits show good accuracy for fault coverage estimates and a computation time linear in the number of gates and comparable to that of the fault-free simulation. >

[1]  A. Lioy.  Adaptative backtrace and dynamic partitioning enhance ATPG (IC testing) , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[2]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[3]  Kurt Antreich,et al.  Accelerated Fault Simulation and Fault Grading in Combinational Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Premachandran R. Menon,et al.  Critical path tracing in sequential circuits , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[5]  Wuudiann Ke,et al.  A fast fault simulation algorithm for combinational circuits , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[6]  A. Lioy.  ADAPTATIVE BACKTRACE AND DYNAMIC PARTITIONING ENHANCE ATPG , 1988 .

[7]  P. R. Menon,et al.  Critical Path Tracing: An Alternative to Fault Simulation , 1984, IEEE Des. Test.

[8]  Janusz Rajski,et al.  A fault simulation method based on stem regions , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.