Design of an oc-192 flow monitoring chip

Being able to monitoring network traffic passing through a router in the internet today very challenging, yet important task. The number of independent flows, which we will define source-destination pair, traversing the internet is growing very rapidly. In recent studies, the ber of separate flows in a one hour period monitored across large ASs has increased into t lions, and will mostly likely continue to grow. The speed of network links is also rapidly increasing, reducing the amount of time available to do memory lookups and making it unfea to use network processor/DRAM based techniques to monitor the flows. When line speeds OC-192 and higher, due to these timing limitation, there will need to be dedicated hardware SRAM to maintain the flow counters. Since SRAM is quite expensive, it will be impossible t track the exact number of bytes sent from each of the million flows passing through a given ro Instead, the goal of this chip is to identify those flows taking up the largest percentages of t bandwidth and do accounting on only these. Tracking the bandwidth usage of just the largest flows will allow several important ne work administrative tasks to be carried out. These include usage-based pricing (if the usag greater than a certain threshold), queue management based upon penalizing over-subscrib users, and detection of denial of service attacks. The design of this chip is based upon the architecture described in the paper, “Scala Measurement: Finding some Elephants in a Swarm of Ants” by Christian Estan and Georg Varghese. In Section 2, I will describe the general architectural implementation. Section 3 w discuss the features and low level design details. Section 4 will discuss a simulation which run to verify the functional correctness and Section 5 will finish with some ideas for future w