A picosecond-accuracy, 700-MHz range, Si bipolar time interval counter LSI

A picosecond-accuracy digital vernier-based single-chip time interval counter (TIC) LSI applicable to timing calibration in state-of-the-art high-speed LSI test systems is described. Jitter performance is improved to three times higher than in conventional circuitry by using a new skew detection circuit that is insensitive to the jitter caused by metastable transitions in flip-flops. All the hardware except the signal sources has been integrated on a Si bipolar 2.5 K gate array LSI by developing fully digitally processes heat-signal and trigger control circuits. The chip is mounted on a dedicated ceramic package employing coplanar lines with a 3-GHz bandwidth. Overall performance achieves 2.3-ps standard deviation, +or-3-ps linearity, zero-skew offset of +or-2.7 ps, and an equivalent input slew time of 33.6 ps/V at input clock rates up to 700 MHz. >

[1]  Timo Rahkonen,et al.  The use of stabilized CMOS delay lines in the digitization of short time intervals , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[2]  A. T. Yang,et al.  Physical timing modeling for bipolar VLSI , 1992 .

[3]  Yukio Akazawa,et al.  Si bipolar 2-GHz 6-bit flash A/D conversion LSI , 1988 .

[4]  T. Rahkonen,et al.  Time interval measurements using time-to-voltage conversion with built-in dual-slope A/D conversion , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[5]  Marc Rocchi.  High-speed digital IC technologies , 1990 .

[6]  Taiichi Otsuji,et al.  Key technologies for 500-MHz VLSI test system ultimate , 1988 .

[7]  D. Porat,et al.  Review of Sub-Nanosecond Time-Interval Measurements , 1973 .

[8]  Toshio Tamamura.  Video DAC/ADC Dynamic Testing , 1986, ITC.

[9]  H. Ichino,et al.  An 80ps 2500-gate bipolar macrocell array , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  Tadashi Sakai,et al.  Gigabit logic bipolar technology: advanced super self-aligned process technology , 1983 .

[11]  J. Van der Spiegel,et al.  A time-to-voltage converter and analog memory for colliding beam detectors , 1989 .

[12]  Taiichi Otsuji.  A Picosecond Accuracy Timing Error Compensation Technique in TDR Measurement , 1991, 1991, Proceedings. International Test Conference.

[13]  Gerard N. Stenbakken,et al.  LINEAR ERROR MODELING OF ANALOG AND MIXED-SIGNAL DEVICES , 1991, 1991, Proceedings. International Test Conference.

[14]  T. Matsumura,et al.  A CMOS four-channel*1K time memory LSI with 1-ns/b resolution , 1992 .

[15]  Taiichi Otsuji,et al.  Key technologies for 500-MHz VLSI system ULTIMATE , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[16]  Taiichi Otsuji,et al.  A 3-ns range, 8-ps resolution, timing generator LSI utilizing Si bipolar gate array , 1991 .

[17]  Y. Yamaguchi,et al.  A high resolution time measurement system , 1991, [1991] Conference Record. IEEE Instrumentation and Measurement Technology Conference.

[18]  J. H. Atherton,et al.  An offset reduction technique for use with CMOS integrated comparators and amplifiers , 1992 .