A CMOS low power, wide dynamic range RSSI with integrated AGC loop

A low voltage low power CMOS limiter and received signal strength indicator (RSSI) with integrated automatic gain control (AGC) loop are designed using TSMC 0.13um CMOS technology. The limiter uses six-stage amplifier architecture for minimum power consideration achieves 56dB gain and 17MHz bandwidth. The RSSI has a dynamic range more than 60dB, and the RSSI linearity error is within ±0.5dB for an input power from −65dBm to −8dBm. The RSSI output voltage is from 0.2V to 1V and the slope of the curve is 14.28mV/dB. The RSSI with integrated AGC loop draws 1.5 mA (I and Q paths) from a 1.2V single supply, including limiters, RSSI and comparators.

[1]  Roubik Gregorian,et al.  Introduction to CMOS OP-AMPs and Comparators , 1999 .

[2]  Renuka P. Jindal.  Gigahertz-band high-gain low-noise AGC amplifiers in fine-line NMOS , 1987 .

[3]  Hen-Wai Tsao,et al.  A 110-MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function , 2005 .

[4]  A.A. Abidi,et al.  A CMOS limiting amplifier and signal-strength indicator , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

[5]  Hen-Wai Tsao,et al.  A 110-MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function , 2005, IEEE Journal of Solid-State Circuits.

[6]  Mohammed Ismail,et al.  CMOS limiters with RSSIs for Bluetooth receivers , 2001, Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257).

[7]  Chorng-Kuang Wang,et al.  A 2-V 10.7-MHz CMOS limiting amplifier/RSSI , 2000, IEEE Journal of Solid-State Circuits.