Emerging nanoscale silicon devices taking advantage of nanostructure physics

This paper describes the present status of research on emerging nanoscale silicon devices that take full advantage of new physical phenomena which appear in silicon nanostructures. This new physics includes quantum effects that enhance the performance of MOS transistors and single-electron charging effects that add new function to conventional CMOS circuits. These physical phenomena may be used to extend the scaling and performance limits of conventional CMOS.

[1]  H. Sakaki,et al.  Interface roughness scattering in GaAs/AlAs quantum wells , 1987 .

[2]  Gold.  Electronic transport properties of a two-dimensional electron gas in a silicon quantum-well structure at low temperature. , 1987, Physical review. B, Condensed matter.

[3]  C. Fiegna,et al.  Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions , 1993, Proceedings of IEEE International Electron Devices Meeting.

[4]  Yasuo Takahashi,et al.  Fabrication technique for Si single-electron transistor operating at room temperature , 1995 .

[5]  Sandip Tiwari,et al.  A silicon nanocrystals based memory , 1996 .

[6]  Toshiro Hiramoto,et al.  Quantum mechanical effects in the silicon quantum dot in a single-electron transistor , 1997 .

[7]  Toshiro Hiramoto,et al.  Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals , 1998 .

[8]  T. Hiramoto,et al.  Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET's , 2000, IEEE Electron Device Letters.

[9]  G. Dewey,et al.  30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[10]  T. Hiramoto,et al.  Impact of quantum mechanical effects on design of nano-scale narrow channel n- and p-type MOSFETs , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[11]  Tadashi Shibata,et al.  Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology , 2001, NIPS.

[12]  Qi Xiang,et al.  15 nm gate length planar CMOS transistor , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[13]  Masumi Saitoh,et al.  Transport spectroscopy of the ultrasmall silicon quantum dot in a single-electron transistor , 2001 .

[14]  T. Numata,et al.  Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm , 2002, Digest. International Electron Devices Meeting,.

[15]  H.-S.P. Wong,et al.  Extreme scaling with ultra-thin Si channel MOSFETs , 2002, Digest. International Electron Devices Meeting,.

[16]  P. Solomon,et al.  Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness , 2003 .

[17]  A. Ogura,et al.  Sub-10-nm planar-bulk-CMOS devices using lateral junction control , 2003, IEEE International Electron Devices Meeting 2003.

[18]  A. Toriumi,et al.  In-plane mobility anisotropy and universality under uni-axial strains in nand p-MOS inversion layers on (100), [110], and (111) Si , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[19]  T. Hiramoto,et al.  Room-temperature demonstration of integrated silicon single-electron transistor circuits for current switching and analog pattern matching , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[20]  I. Aberg,et al.  High electron and hole mobility enhancements in thin-body strained Si/strained SiGe/strained Si heterostructures on insulator , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[21]  T. Tezuka,et al.  Selectively-formed high mobility SiGe-on-Insulator pMOSFETs with Ge-rich strained surface channels using local condensation technique , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[22]  Masumi Saitoh,et al.  Room-temperature demonstration of highly-functional single-hole transistor logic based on quantum mechanical effect , 2004 .

[23]  Masumi Saitoh,et al.  Extension of Coulomb blockade region by quantum confinement in the ultrasmall silicon dot in a single-hole transistor at room temperature , 2004 .

[24]  T. Hiramoto,et al.  Scaling of nanocrystal memory cell by direct tungsten bitline on self-aligned landing plug polysilicon contact , 2004, IEEE Electron Device Letters.

[25]  Masumi Saitoh,et al.  Room-Temperature Operation of Current Switching Circuit Using Integrated Silicon Single-Hole Transistors , 2005 .

[26]  Masumi Saitoh,et al.  Superior mobility characteristics in [110]-oriented ultra thin body pMOSFETs with SOI thickness less than 6 nm , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[27]  Masumi Saitoh,et al.  Very Sharp Room-Temperature Negative Differential Conductance in Silicon Single-Hole Transistor with High Voltage Gain , 2005 .

[28]  T. Hiramoto,et al.  Experimental study on superior mobility in [110]-oriented UTB SOI pMOSFETs , 2005, IEEE Electron Device Letters.

[29]  Masumi Saitoh,et al.  Voltage gain dependence of the negative differential conductance width in silicon single-hole transistors , 2006 .