Pattern sensitive placement for manufacturability

When VLSI technology scales toward 45nm, the lithography wavelength stays at 193nm. This large gap results in strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features on wafers and the printing is more susceptible to lithographic process variations. Although resolution enhancement techniques can mitigate this manufacturability problem, their capabilities are overstretched by the continuous shrinking of VLSI feature size. On the other hand,the quality and robustness of lithography directly depend on layout patterns. Therefore, it becomes imperative to consider the manufacturability issue during layout design such that the burden of lithography process can be alleviated. In this paper, the problem of cell placement considering manufacturability is studied. Instead of designing a new cellplacer, our goal is to tune any existing cell placement solution to be lithography friendly. For this purpose, three algorithms are proposed, which are cell flipping algorithm, single row optimization approach and multiple row optimization approach. These algorithms are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between edge placement error (EPE)reduction and wirelength increase. Using lithography simulations, our experimental results on realistic netlists and cell library demonstrate that over 20% EPE reduction can be obtained by thenew approaches while only less than 1% additional wire is introduced.