C/C++ etc.-Based Design Flows

This chapter focuses on C/C++ flows in the context of generic digital designs. It discusses the problems with traditional hardware description languages (HDL)-based flows. It briefly summarizes what systemC is and systemC-based flows have been considered. There is a wide variety of programming languages available, the most commonly used are traditional C and its object-oriented offspring C+ +. Statements in languages like C/C++ are executed sequentially. Standard C/C++ can be augmented to extend its capabilities and the things it can be used to represent. In the case of capturing the functionality of hardware for ASIC and FPGA designs, it is necessary to augment standard C/C++ with special statements to support concepts as such clocks, pins, concurrency, synchronization, and resource sharing. In the case of a design that begins life as a suite of algorithms, it is very common to start by creating a C or C++ representation. In the case of the hardware description language HDL)-based flows, this C/C++ representation of the algorithms would then be hand-translated into RTL VHSIC hardware description language VHDL)/Verilog. The C/C++ representation will typically continue to be used as a golden model, which means it can be linked into the RTL simulator and run in parallel with the RTL simulation. The results from the C/C++ and RTL models can be compared to ensure that they are functionally equivalent.