A Flexible Heterogeneous Video Processor System For Television Applications.

A new video processing architecture for high-end TV applications is presented, featuring a flexible heterogeneous multi-processor architecture, executing video tasks in parallel and independently. The signal flow graph and the processors are programmable, enabling an optimal picture quality for different TV display modes. The concept is verified by an experimental chip design. The architecture allows several video streams to be processed and displayed in parallel and in a programmable way, with an individual signal quality.

[1]  P. H. Lindsay.  Human Information Processing , 1977 .

[2]  J. Veerhoek,et al.  Economy Picture-in-picture Processor , 1998, International 1998 Conference on Consumer Electronics.

[3]  O. Popp,et al.  A 1.5 GIPS video signal processor (VSP) , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[4]  Edward A. Lee,et al.  Scheduling dynamic dataflow graphs with bounded memory using the token flow model , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[5]  Gilles Kahn,et al.  The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.

[6]  A. Papoulis.  Systems and transforms with applications in optics , 1981 .

[7]  Egbert G. T. Jaspers,et al.  A generic 2D sharpness enhancement algorithm for luminance signals , 1997 .

[8]  J.G.W.M. Janssen,et al.  An advanced sampling rate conversion technique for video and graphics signals , 1997 .