论文信息 - A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE - 字舞流文

A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE

APE100 processors are based on a simple Single Instruction Multiple Data architecture optimized for the simulation of Lattice Field Theories or other complex physical systems. This paper describes the hardware implementation of the first APE100 machine.

Raffaele Tripiccione | P. Paolucci | Piero Vicini | Emanuele Panizzi | A. Bartoloni | C. Battista | Simone Cabasino | Nicola Cabibbo | Federico Rapuano | R. Sarno | G. M. Todesco | M. Torelli | A. Fucci | G. Bastianello | Francesco Marzano | J. Pech | W. Tross | F. Marzano | P. Vicini | N. Cabibbo | R. Tripiccione | J. Pech | A. Fucci | S. Cabasino | P. Paolucci | M. Torelli | F. Rapuano | R. Sarno | G. Todesco | W. Tross | E. Panizzi | A. Bartoloni | C. Battista | G. Bastianello | Emanuele Panizzi