Quasi-complementary BiCMOS for sub-3-V digital circuits
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Takashi Nishida | Katsuhiro Shimohigashi | Mitsuru Hiraki | Koichi Seki | K. Yano | Shoji Shukuri | Y. Onose | Mitsuru Hirao | N. Ohki
[1] Lynn Conway,et al. Introduction to VLSI systems , 1978 .
[2] Y. Ohji,et al. High field effects in MOSFETS , 1985, 1985 International Electron Devices Meeting.
[3] H. C. Poon,et al. An integral charge control model of bipolar transistors , 1970, Bell Syst. Tech. J..
[4] G. P. Rosseel,et al. Influence of device parameters on the switching speed of BiCMOS buffers , 1989 .
[5] H. J. Shin,et al. Performance comparison of driver configurations and full-swing techniques for BiCMOS logic circuits , 1990 .
[6] Minoru Fujishima,et al. Evaluation of delay-time degradation of low-voltage BiCMOS based on a novel analytical delay-time modeling , 1991 .
[7] S. M. Sze,et al. Physics of semiconductor devices , 1969 .
[8] Makoto Suzuki,et al. A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.
[9] Atsuo Watanabe,et al. Future BiCMOS technology for scaled supply voltage , 1989, International Technical Digest on Electron Devices Meeting.
[10] Robert G. Meyer,et al. Analysis and Design of Analog Integrated Circuits , 1993 .
[11] Kazuo Yano,et al. PARAMOST - A New Parasitic Resistance Model for Deep Submicron MOS Transistors , 1986 .
[12] H.J. Shin. Full-swing logic circuits in a complementary BiCMOS technology , 1990, Digest of Technical Papers., 1990 Symposium on VLSI Circuits.
[13] C.-L. Chen,et al. Full-swing complementary BiCMOS logic circuits , 1989, Proceedings of the Bipolar Circuits and Technology Meeting.
[14] T. Ikeda,et al. Performance and structures of scaled-down bipolar devices merged with CMOSFETs , 1984, 1984 International Electron Devices Meeting.
[15] Goro Kitsukawa,et al. A 23-ns 1-Mb BiCMOS DRAM , 1990 .
[16] H. Momose,et al. 0.5 Micron BICMOS technology , 1987, 1987 International Electron Devices Meeting.