On the Universality of Multipath Multistage Interconnection Networks

Abstract An analytic approximation for the blocking probability of a circuit-switched, multipath multistage interconnection network when it is required to perform arbitrary permutations under local control is presented. An analytic approximation for the expected number of conflict-free permutations realizable by a network in one pass under local control is also presented. In addition, an analytic approximation for the expected number of passes through a network required to realize an arbitrary permutation under local control is presented. These models give a quantitative measure of a network's ability to perform arbitrary permutations and of the inherent blocking in a network. These models are used to analyze two variations of banyan networks that have been discussed in the literature: dilated and augmented banyan networks. It is shown that these networks can be designed with very low blocking probabilities under permutation request patterns, and that they can be designed to realize almost all permutations in one pass under local control.

[1]  Miroslaw Malek,et al.  On the Number of Permutations Performable by Extra-Stage Multistage Interconnection Networks , 1989, IEEE Trans. Computers.

[2]  Miroslaw Malek,et al.  On Permuting Properties of Regular Rectangular SW-Banyans , 1985, IEEE Transactions on Computers.

[3]  Dharma P. Agrawal,et al.  Design and Performance of Generalized Interconnection Networks , 1983, IEEE Transactions on Computers.

[4]  Viktor K. Prasanna,et al.  Permutations on Illiac IV-Type Networks , 1986, IEEE Transactions on Computers.

[5]  V. Benes,et al.  Mathematical Theory of Connecting Networks and Telephone Traffic. , 1966 .

[6]  Allan Gottlieb,et al.  Networks and algorithms for very-large-scale parallel computation , 2011, Computer.

[7]  Mark A. Franklin,et al.  VLSI Performance Comparison of Banyan and Crossbar Communications Networks , 1981, IEEE Transactions on Computers.

[8]  Leslie G. Valiant,et al.  A fast parallel algorithm for routing in permutation networks , 1981, IEEE Transactions on Computers.

[9]  Howard Jay Siegel,et al.  Analysis Techniques for SIMD Machine Interconnection Networks and the Effects of Processor Address Masks , 1977, IEEE Transactions on Computers.

[10]  Cauligi S. Raghavendra,et al.  Realization of permutations on generalized INDRA networks , 1988, Inf. Sci..

[11]  Jacques Lenfant,et al.  Parallel Permutations of Data: A Benes Network Control Algorithm for Frequently Used Permutations , 1978, IEEE Transactions on Computers.

[12]  Charles Clos,et al.  A study of non-blocking switching networks , 1953 .

[13]  Duncan H. Lawrie,et al.  Access and Alignment of Data in an Array Processor , 1975, IEEE Transactions on Computers.

[14]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[15]  Paul Budnik,et al.  The Organization and Use of Parallel Memories , 1971, IEEE Transactions on Computers.

[16]  Duncan H. Lawrie,et al.  The Prime Memory System for Array Access , 1982, IEEE Transactions on Computers.

[17]  Mary Diane Palmer Leland.  On the Power of the Augmented Data Manipulator Network , 1985, ICPP.

[18]  Chuan-lin Wu,et al.  Tutorial, interconnection networks for parallel and distributed processing , 1984 .

[19]  Janak H. Patel.  Performance of Processor-Memory Interconnections for Multiprocessors , 1981, IEEE Transactions on Computers.

[20]  Tse-Yun Feng,et al.  The Universality of the Shuffle-Exchange Network , 1981, IEEE Transactions on Computers.

[21]  Mark A. Franklin,et al.  Pin Limitations and Partitioning of VLSI Interconnection Networks , 1982, IEEE Transactions on Computers.

[22]  Douglas Stott Parker,et al.  Notes on Shuffle/Exchange-Type Switching Networks , 1980, IEEE Transactions on Computers.

[23]  Luigi Ciminiera,et al.  A Connecting Network with Fault Tolerance Capabilities , 1986, IEEE Transactions on Computers.

[24]  Gerald M. Masson,et al.  A Sampler of Circuit Switching Networks , 1979, Computer.

[25]  Ian F. Blake.  An Introduction to Applied Probability , 1981 .

[26]  Pen-Chung Yew.  On the design of interconnection networks for parallel and multiprocessor systems , 1981 .

[27]  Allan Gottlieb,et al.  Complexity Results for Permuting Data and Other Computations on Parallel Processors , 1984, JACM.

[28]  Mary-Diane Palmer Leland.  Properties and comparison of multistage interconnection networks for simd machines , 1983 .

[29]  Ted H. Szymanski,et al.  On the Permutation Capability of Multistage Interconnection Networks , 1987, IEEE Transactions on Computers.

[30]  Tomás Lang,et al.  Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network , 1976, IEEE Transactions on Computers.

[31]  Sartaj Sahni,et al.  A Self-Routing Benes Network and Parallel Permutation Algorithms , 1981, IEEE Transactions on Computers.

[32]  Ted H. Szymanski,et al.  On the Universality of Multistage Interconnection Networks , 1986, International Conference on Parallel Processing.

[33]  Cauligi S. Raghavendra,et al.  The Gamma network: A multiprocessor interconnection network with redundant paths , 1982, ISCA 1982.

[34]  D. C. Opferman,et al.  On a class of rearrangeable switching networks part I: Control algorithm , 1971 .

[35]  Howard Jay Siegel,et al.  The universality of various types of SIMD machine interconnection networks , 1977, ISCA '77.

[36]  Kai Hwang,et al.  Hypernet: A Communication-Efficient Architecture for Constructing Massively Parallel Computers , 1987, IEEE Transactions on Computers.

[37]  Abraham Waksman,et al.  A Permutation Network , 1968, JACM.

[38]  Kyungsook Y. Lee.  On the Rearrangeability of 2(log2N) - 1 Stage Permutation Networks , 1985, IEEE Trans. Computers.

[39]  David G. Cantor,et al.  On non-blocking switching networks , 1971, Networks.

[40]  Shing-Tsaan Huang,et al.  Finite State Model and Compatibility Theory: New Analysis Tools for Permutation Networks , 1986, IEEE Transactions on Computers.

[41]  Ted H. Szymanski.  Interconnection Network Modelling Using Monte Carlo Methods, Markov Chains and Performance Petri Nets , 1987, Computer Performance and Reliability.

[42]  Marc Snir,et al.  The Performance of Multistage Interconnection Networks for Multiprocessors , 1983, IEEE Transactions on Computers.

[43]  Dharma P. Agrawal,et al.  Graph Theoretical Analysis and Design of Multistage Interconnection Networks , 1983, IEEE Transactions on Computers.

[44]  Manoj Kumar,et al.  Generalized Delta Networks , 1983, ICPP.

[45]  Tse-Yun Feng,et al.  The Reverse-Exchange Interconnection Network , 1980, IEEE Trans. Computers.

[46]  Stephen F. Lundstrom,et al.  Design and Validation of a Connection Network for Many-Processor Multiprocessor Systems , 1981, Computer.

[47]  David Steinberg.  Invariant Properties of the Shuffle-Exchange and a Simplified Cost-Effective Version of the Omega Network , 1983, IEEE Transactions on Computers.

[48]  Duncan H. Lawrie,et al.  A Class of Redundant Path Multistage Interconnection Networks , 1983, IEEE Transactions on Computers.

[49]  Howard Jay Siegel,et al.  On the Number of Permutations Performable by the Augmented Data Manipulator Network , 1982, IEEE Transactions on Computers.