Computationally efficient active rule detection method: Algorithm and architecture

In this paper, a new active rule detection algorithm is proposed which is efficiently implemented in dedicated fuzzy processors. Here, its advantages are analytically attested. A novel realization architecture is proposed that has higher performance and uses lower hardware resources in comparison to the other reported architectures. The structure of the proposed active rule detection unit is scalable in terms of the number of inputs, the number of membership functions and their bit widths. The proposed architecture is flexible in term of membership function shape as well.

[1]  Lotfi A. Zadeh,et al.  Fuzzy logic, neural networks, and soft computing , 1993, CACM.

[2]  H. Ikeda,et al.  A fuzzy inference coprocessor using a flexible active-rule-driven architecture , 1992, [1992 Proceedings] IEEE International Conference on Fuzzy Systems.

[3]  Norman P. Jouppi,et al.  Readings in computer architecture , 2000 .

[4]  Roberto Lojacono,et al.  VLSI implementation of a real time fuzzy processor , 1998, J. Intell. Fuzzy Syst..

[5]  Sied Mehdi Fakhraie,et al.  Cost-Performance Co-Analysis in VLSI Implementation of Existing and New Defuzzification Methods , 2005, International Conference on Computational Intelligence for Modelling, Control and Automation and International Conference on Intelligent Agents, Web Technologies and Internet Commerce (CIMCA-IAWTIC'06).

[6]  Norman P. Jouppi,et al.  CACTI 2.0: An Integrated Cache Timing and Power Model , 2002 .

[7]  Chuen-Chien Lee FUZZY LOGIC CONTROL SYSTEMS: FUZZY LOGIC CONTROLLER - PART I , 1990 .

[8]  Pao-Ta Yu,et al.  Weighted fuzzy mean filters for heavy-tailed noise removal , 1995, Proceedings of 3rd International Symposium on Uncertainty Modeling and Analysis and Annual Conference of the North American Fuzzy Information Processing Society.

[9]  James C. Bezdek,et al.  Validity-guided (re)clustering with applications to image segmentation , 1996, IEEE Trans. Fuzzy Syst..

[10]  Shih-Hsu Huang,et al.  A high speed fuzzy inference processor with dynamic analysis and scheduling capabilities , 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

[11]  R. d'Amore A bit scalable architecture for fuzzy processors with three inputs and a flexible fuzzification unit , 2000, Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843).

[12]  Norman P. Jouppi,et al.  CACTI: an enhanced cache access and cycle time model , 1996, IEEE J. Solid State Circuits.

[13]  Lotfi A. Zadeh,et al.  Outline of a New Approach to the Analysis of Complex Systems and Decision Processes , 1973, IEEE Trans. Syst. Man Cybern..

[14]  Rogelio Palomera-Garcia,et al.  A high speed scalable and reconfigurable fuzzy controller , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[15]  Caro Lucas,et al.  Soft Real-Time Fuzzy Task Scheduling for Multiprocessor Systems , 2007 .

[16]  Alessandro De Gloria,et al.  Fuzzy logic microcontroller , 1997, IEEE Micro.

[17]  Enrique Frias-Martinez,et al.  Real-time fuzzy processor on a DSP , 2001, ETFA 2001. 8th International Conference on Emerging Technologies and Factory Automation. Proceedings (Cat. No.01TH8597).

[18]  G. Amdhal,et al.  Validity of the single processor approach to achieving large scale computing capabilities , 1967, AFIPS '67 (Spring).

[19]  I. Kalaykov,et al.  DSP-BASED FAST FUZZY LOGIC CONTROLLERS , 2000 .

[20]  Angel Barriga,et al.  HARDWARE IMPLEMENTATION OF A GENERAL PURPOSE FUZZY CONTROLLER , 1995 .

[21]  T. Wada,et al.  An analytical access time model for on-chip cache memories , 1992 .

[22]  Bogdan M. Wilamowski,et al.  Implementing a fuzzy system on a field programmable gate array , 2001, IJCNN'01. International Joint Conference on Neural Networks. Proceedings (Cat. No.01CH37222).

[23]  Haridimos T. Vergos,et al.  On the Yield of VLSI Processors with on-chip CPU Cache , 1996, EDCC.

[24]  Nadia Nedjah,et al.  Evolvable machines : theory & practice , 2005 .

[25]  G. Ascia,et al.  A pipeline parallel architecture for a fuzzy inference processor , 2000, Ninth IEEE International Conference on Fuzzy Systems. FUZZ- IEEE 2000 (Cat. No.00CH37063).

[26]  Osamu Saotome,et al.  A Two-Input, One-Output Bit-Scalable Architecture for Fuzzy Processors , 2001, IEEE Des. Test Comput..

[27]  Shuta Murakami,et al.  The use of a fuzzy decision-making method in a large-scale computer system choice problem , 1993 .

[28]  Sied Mehdi Fakhraie,et al.  Hardware implementation and comparison of new defuzzification techniques in fuzzy processors , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[29]  Valentina Salapura,et al.  A fuzzy RISC processor , 2000, IEEE Trans. Fuzzy Syst..

[30]  Michael J. Flynn,et al.  An area model for on-chip memories and its application , 1991 .

[31]  Zhang Xun,et al.  VLSI design and implementation of a fuzzy logic controller for engine idle speed , 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

[32]  José Luis Martín,et al.  Hardware implementation of a pipeline fuzzy controller and software tools , 2002, Fuzzy Sets Syst..

[33]  Chiung-San Lee,et al.  High speed multistage fuzzy hardware architecture for fuzzy logic control , 2000, Smc 2000 conference proceedings. 2000 ieee international conference on systems, man and cybernetics. 'cybernetics evolving to systems, humans, organizations, and their complex interactions' (cat. no.0.

[34]  Sied Mehdi Fakhraie,et al.  Software Implementation Issues of Existing and New Defuzzification Methods , 2006, 2006 IEEE International Conference on Fuzzy Systems.

[35]  Daniela Panno,et al.  A VLSI fuzzy expert system for real-time traffic control in ATM networks , 1997, IEEE Trans. Fuzzy Syst..

[36]  Vincenzo Catania,et al.  A general purpose processor oriented to fuzzy reasoning , 2001, 10th IEEE International Conference on Fuzzy Systems. (Cat. No.01CH37297).

[37]  H. Watanabe,et al.  A fuzzy logic controller with reconfigurable, cascadable architecture , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[38]  Abraham Kandel,et al.  Fuzzy hardware: architectures and applications , 1997 .

[39]  Edwin Hsing-Mean Sha,et al.  Rapid prototyping for fuzzy systems , 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

[40]  Rudolf Kruse,et al.  Fuzzy Systems , 2010, Encyclopedia of Machine Learning.

[41]  Alessandro Gabrielli,et al.  Very fast rate 2-input fuzzy processor for high energy physics , 2002, Fuzzy Sets Syst..

[42]  Herman Schmit,et al.  Synthesis of application-specific memory designs , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[43]  Norman P. Jouppi,et al.  Cacti 3. 0: an integrated cache timing, power, and area model , 2001 .

[44]  Lotfi A. Zadeh,et al.  Fuzzy Logic , 2009, Encyclopedia of Complexity and Systems Science.