Asymmetrically Doped FinFETs for Low-Power Robust SRAMs

We propose FinFETs with unequal source and drain doping concentrations [asymmetrically doped (AD) FinFETs] for low-power robust SRAMs. The effect of asymmetric source/drain doping on the device characteristics is extensively analyzed, and the key differences between conventional and AD FinFETs are clearly shown. We show that asymmetry in the device structure leads to unequal currents for positive and negative drain biases, which is exploited to achieve mitigation of read-write conflict in 6T SRAMs. The proposed device exhibits superior short-channel characteristics compared to a conventional FinFET due to reduced electric fields from the terminal that has a lower doping. This results in significantly lower cell leakage in AD-FinFET-based 6T SRAM. Compared to the conventional FinFET-based 6T SRAM, AD-FinFET SRAM shows 5.2%-8.3% improvement in read static noise margin (SNM), 4.1%-10.2% higher write margin, 4.1%-8.8% lower write time, 1.3%-3.5% higher hold SNM, and 2.1-2.5 lower cell leakage at the cost of 20%-23% higher access time. There is no area penalty associated with the proposed technique.

[1]  S. Inoue,et al.  A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs , 1989, International Technical Digest on Electron Devices Meeting.

[2]  K. F. Lee,et al.  Scaling the Si MOSFET: from bulk to SOI to bulk , 1992 .

[3]  T. Hori,et al.  A 0.1 /spl mu/m CMOS technology with tilt-implanted punchthrough stopper (TIPS) , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[4]  Chenming Hu,et al.  A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[5]  T. Sugii,et al.  Ultrafast operation of V/sub th/-adjusted p/sup +/-n/sup +/ double-gate SOI MOSFET's , 1994, IEEE Electron Device Letters.

[6]  Thomas A. DeMassa,et al.  Digital Integrated Circuits , 1985, 1985 IEEE GaAs IC Symposium Technical Digest.

[7]  Chenming Hu,et al.  A folded-channel MOSFET for deep-sub-tenth micron era , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[8]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[9]  Chenming Hu,et al.  Nanoscale CMOS spacer FinFET for the terabit era , 2002, IEEE Electron Device Letters.

[10]  Byung-Gook Park,et al.  Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile , 2002 .

[11]  Bing-Yue Tsui,et al.  A comprehensive study on the FIBL of nanoscale MOSFETs , 2004, IEEE Transactions on Electron Devices.

[12]  Bing-Yue Tsui,et al.  A comprehensive study on the FIBL of nanoscale MOSFETs , 2004 .

[13]  K. Bernstein,et al.  Scaling, power, and the future of CMOS , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[14]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[15]  Saibal Mukhopadhyay,et al.  Modeling and optimization approach to robust and low-power FinFET SRAM design in nanoscale era , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[16]  V. Trivedi,et al.  Nanoscale FinFETs with gate-source/drain underlap , 2005, IEEE Transactions on Electron Devices.

[17]  M. Nomura,et al.  Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[18]  Jie Gu,et al.  Width Quantization Aware FinFET Circuit Design , 2006, IEEE Custom Integrated Circuits Conference 2006.

[19]  R. Rooyackers,et al.  Multi-gate devices for the 32nm technology node and beyond , 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

[20]  A.P. Chandrakasan,et al.  A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.

[21]  Mark Horowitz,et al.  Scaling, Power and the Future of CMOS , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[22]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2006, 2007 IEEE International Electron Devices Meeting.

[23]  K. Roy,et al.  Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era , 2007, IEEE Transactions on Electron Devices.

[24]  Hui Zhao,et al.  Analysis of the Effects of Fringing Electric Field on FinFET Device Performance and Structural Optimization Using 3-D Simulation , 2008, IEEE Transactions on Electron Devices.

[25]  Rita Rooyackers,et al.  Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth , 2008 .

[26]  D.K. Sharma,et al.  Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization , 2008, IEEE Electron Device Letters.

[27]  Rita Rooyackers,et al.  Multi-gate devices for the 32 nm technology node and beyond , 2008 .

[28]  Ching-Te Chuang,et al.  Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors , 2009, IEEE Electron Device Letters.

[29]  Zheng Guo,et al.  SRAM Read/Write Margin Enhancements Using FinFETs , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[30]  K. Roy,et al.  Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs , 2011, IEEE Transactions on Electron Devices.