Modeling and Understanding of External Latchup in CMOS Technologies—Part I: Modeling Latchup Trigger Current

This paper elucidates the roles of substrate majority and minority carriers in triggering external latchup, where the term external signifies that the substrate current injection occurs at a location away from the p-n-p-n structure. Circuit-level models are presented that allow one to identify the worst case testing condition and to simulate the value of the latchup trigger current. The model captures the effect of guard rings. The simulation results are compared to measurement results, and good agreement is observed, for a variety of CMOS technologies.

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