ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization

Research in the domain of reversible circuits found significant interest in the last years - not least because of the promising applications e.g. in quantum computation and low-power design. First physical realizations are already available, motivating the development of efficient testing methods for this kind of circuits. In this paper, complementary approaches for automatic test pattern generation for reversible circuits are introduced and evaluated. Besides a simulation-based technique, methods based on Boolean satisfiability and pseudo-Boolean optimization are thereby applied. Experiments on large reversible circuits show the suitability of the proposed approaches with respect to different application scenarios and test goals, respectively.

[1]  J. Hayes,et al.  Fault testing for reversible circuits , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[2]  Robert Wille,et al.  BDD-based synthesis of reversible logic for large functions , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[3]  Tommaso Toffoli,et al.  Reversible Computing , 1980, ICALP.

[4]  Robert Wille,et al.  SAT-based ATPG for reversible circuits , 2010, 2010 5th International Design and Test Workshop.

[5]  John P. Hayes,et al.  A Family of Logical Fault Models for Reversible Circuits , 2005, 14th Asian Test Symposium (ATS'05).

[6]  Martin Gebser,et al.  Conflict-Driven Answer Set Solving , 2007, IJCAI.

[7]  I. Chuang,et al.  Experimental realization of Shor's quantum factoring algorithm using nuclear magnetic resonance , 2001, Nature.

[8]  John P. Hayes,et al.  Testing for missing-gate faults in reversible circuits , 2004, 13th Asian Test Symposium.

[9]  Robert Wille,et al.  RevLib: An Online Resource for Reversible Functions and Reversible Circuits , 2008, 38th International Symposium on Multiple Valued Logic (ismvl 2008).

[10]  Sy-Yen Kuo,et al.  An XQDD-Based Verification Method for Quantum Circuits , 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[11]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[12]  R. Landauer,et al.  Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..

[13]  John P. Hayes,et al.  Checking equivalence of quantum circuits and states , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[14]  Stefan Frehse,et al.  Debugging of Toffoli networks , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[15]  John P. Hayes,et al.  Synthesis of reversible logic circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Thierry Paul,et al.  Quantum computation and quantum information , 2007, Mathematical Structures in Computer Science.

[17]  Peter W. Shor,et al.  Algorithms for quantum computation: discrete logarithms and factoring , 1994, Proceedings 35th Annual Symposium on Foundations of Computer Science.

[18]  D. Michael Miller,et al.  Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits , 2008, 2008 Design, Automation and Test in Europe.

[19]  Niklas Sörensson,et al.  Translating Pseudo-Boolean Constraints into SAT , 2006, J. Satisf. Boolean Model. Comput..

[20]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[21]  Alexis De Vos,et al.  A reversible carry-look-ahead adder using control gates , 2002, Integr..

[22]  Robert Wille,et al.  Reducing Reversible Circuit Cost by Adding Lines , 2010, 2010 40th IEEE International Symposium on Multiple-Valued Logic.