Substrate Resistance Extraction for Physics-based Layout Verification

Resistive coupling effects via the substrate may damage circuit behaviour of VLSI chips. In order to analyze the influence of the substrate on the circuit behaviour of VLSI chips the admittance matrix of the substrate must be known. This paper describes a Boundary Element Method for the calculation of this matrix. The method uses a Green’s function for the bounded 3D medium. The advantage of this approach is that only those parts of the boundary where current passes — such as substrate contacts and transistor bulk contacts — need to be discretized. Some examples of the use of this method are presented for 2D and 3D problems.