Exploring Well-Configurations for Minimizing Single Event Latchup

This work experimentally studies single event latchup (SEL) prevention by altering well configurations. The well structures under consideration in this paper are ordinary twin-well structure, triple-well structure with deep N-well (DNW) and triple-well structure with deep P-well (DPW). Doping profiles are also varied in our experiments. Neutron irradiation tests for test chips fabricated in 55-nm and 90-nm bulk Si CMOS processes show that SEL can be suppressed with a DPW or a DNW well configuration and a high-dose implantation in the well. Among these, DPW was the most effective to eliminate SEL, and no SEL was observed throughout our irradiation tests in the SRAM with DPW in both 55-nm and 90-nm processes. In addition, DPW brings a desirable side effect of single event upset (SEU) reduction. A disadvantage is a cost to develop a DPW process. DNW is a common process option and hence it is easily adopted for SEL prevention, but we need to pay attention to the fact that DNW increases SEU rate. Increasing well doping in twin-well structure reduced SEL by 60%.

[1]  S. S. Chung,et al.  Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling , 2006, IEEE Custom Integrated Circuits Conference 2006.

[2]  Michael Nicolaidis.  A low-cost single-event latchup mitigation scheme , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

[3]  D.R. Czajkowski,et al.  Single event latchup protection of integrated circuits , 1997, RADECS 97. Fourth European Conference on Radiation and its Effects on Components and Systems (Cat. No.97TH8294).

[4]  Yukio Sakamoto,et al.  Evaluation of the White Neutron Beam Spectrum for Single-Event Effects Testing at the RCNP Cyclotron Facility , 2011 .

[5]  P.E. Dodd,et al.  Neutron-induced soft errors, latchup, and comparison of SER test methods for SRAM technologies , 2002, Digest. International Electron Devices Meeting,.

[6]  T. Uemura,et al.  Preventing single event latchup with deep P-well on P-substrate , 2014, 2014 IEEE International Reliability Physics Symposium.

[7]  Paul E. Dodd,et al.  Neutron-induced latchup in SRAMs at ground level , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[8]  P. Dodd,et al.  Radiation effects in SOI technologies , 2003 .

[9]  L W Massengill,et al.  Selection of Well Contact Densities for Latchup-Immune Minimal-Area ICs , 2010, IEEE Transactions on Nuclear Science.

[10]  Stephen LaLumondiere,et al.  A single event latchup suppression technique for COTS CMOS ICs , 2003 .

[11]  Marty R. Shaneyfelt,et al.  Impact of substrate thickness on single-event effects in integrated circuits , 2001 .

[12]  A. Johnston,et al.  Latent damage in CMOS devices from single-event latchup , 2002 .

[13]  Jae-Eul Yeon,et al.  A new high voltage shorted-anode IGBT with intrinsic body diode improves performance of single-ended induction cooker , 2013, 2013 15th European Conference on Power Electronics and Applications (EPE).

[14]  R. G. Useinov,et al.  Analytical Model of Radiation Induced or Single Event Latchup in CMOS Integrated Circuits , 2006, IEEE Transactions on Nuclear Science.

[15]  E. Gebreselasie,et al.  Latchup in merged triple well structure , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[16]  T. Aoki,et al.  Dynamics of heavy-ion-induced latchup in CMOS structures , 1988 .

[17]  G. Gasiot,et al.  Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering , 2007, IEEE Transactions on Nuclear Science.

[18]  D. K. Nichols,et al.  Latchup in CMOS Devices from Heavy Ions , 1983, IEEE Transactions on Nuclear Science.

[19]  G. Bruguier,et al.  Single particle-induced latchup , 1996 .

[20]  H. Puchner,et al.  Elimination of Single Event Latchup in 90nm SRAM Technologies , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[21]  A. N. Smirnov,et al.  ANITA — a new neutron facility for accelerated SEE testing at the svedberg laboratory , 2009, 2009 IEEE International Reliability Physics Symposium.

[22]  Allan H. Johnston,et al.  The influence of VLSI technology evolution on radiation-induced latchup in space systems , 1996 .

[23]  Analytical Model of Radiation Induced or Single Event Latchup in CMOS Integrated Circuits , 2005, 2005 8th European Conference on Radiation and Its Effects on Components and Systems.

[24]  D. S. Walsh,et al.  SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments , 2001 .