Above-threshold drain current model including band tail states in nanocrystalline silicon thin-film transistors for circuit implementation

A simple analytical expression for the above threshold voltage drain current is derived in nanocrystalline silicon thin-film transistors (TFTs), based on an exponential energy distribution of band tail states. When the characteristic temperature distribution of the band tails is equal to 1.5 times the lattice temperature, the derived expression leads to the basic “quadratic” metal-oxide-semiconductor current expression. By including the impact ionization effect and using the same trap distribution parameters, the model describes adequately the output characteristics of TFTs with different channel dimensions, making the proposed model suitable for the design of circuits with nc-Si TFTs.

[1]  M. Shur,et al.  New high field‐effect mobility regimes of amorphous silicon alloy thin‐film transistor operation , 1986 .

[2]  A. J. Lowe,et al.  Determination of bulk states and interface states distributions in polycrystalline silicon thin‐film transistors , 1993 .

[3]  T. Ytterdal,et al.  DC SPICE model for nanocrystalline and microcrystalline silicon TFTs , 2002 .

[4]  Krishna C. Saraswat,et al.  A strategy for modeling of variations due to grain size in polycrystalline thin-film transistors , 2000 .

[5]  Regis Vanderhaghen,et al.  Stable microcrystalline silicon thin-film transistors produced by the layer-by-layer technique , 1999 .

[6]  K. Saraswat,et al.  Determination of the densities of gap states in hydrogenated polycrystalline Si and Si0.8Ge0.2 films , 1992 .

[7]  D. Dosev Device simulations of nanocrystalline silicon thin-film transistors , 2003 .

[8]  M. J. Powell,et al.  Dangling-bond defect state creation in microcrystalline silicon thin-film transistors , 2000 .

[9]  S. B. Herner,et al.  On the conduction mechanism in polycrystalline silicon thin-film transistors , 2004, IEEE Transactions on Electron Devices.

[10]  S. Wagner,et al.  Hole and electron field-effect mobilities in nanocrystalline silicon deposited at 150°C , 2002 .

[11]  H. Kuwano,et al.  Energy distribution of trapping states at grain boundaries in polycrystalline silicon , 1992 .

[12]  Jordi Andreu,et al.  Microcrystalline silicon thin film transistors obtained by hot-wire CVD , 2000 .

[13]  Arokia Nathan,et al.  High-mobility nanocrystalline silicon thin-film transistors fabricated by plasma-enhanced chemical vapor deposition , 2005 .

[14]  François Templier,et al.  Electrical and noise characterization of bottom-gated nanocrystalline silicon thin-film transistors , 2006 .

[15]  G. Neudeck,et al.  A simplified model for the static characteristics of amorphous silicon thin-film transistors , 1986 .

[16]  J. B. Kuo,et al.  An analytical moderate inversion drain current model for polycrystalline silicon thin‐film transistors considering deep and tail states in the grain boundary , 1996 .

[17]  Antonio Cerdeira,et al.  Modeling and parameter extraction procedure for nanocrystalline TFTs , 2004 .

[18]  Jordi Andreu,et al.  Thin film transistors obtained by hot wire CVD , 2000 .

[19]  C. A. Dimitriadis,et al.  Effects of hydrogenation on the performance and stability of p-channel polycrystalline silicon thin-film transistors , 2003, Microelectron. Reliab..