Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems

This paper presents the design and analysis of a power and area efficient transpose memory structure for use in adaptive signal processing systems. The proposed architecture achieves significant improvements in system throughput over competing designs. We demonstrate the throughput performance of the proposed memory on FPGA as well as ASIC implementations. The memory was employed in a watermarking architecture previously proposed. The new memory design allows for 2X speed up in performance for the watermarking algorithm and up to 10X speedup for 2D DCT and IDCT algorithms compared to previously published work, while consuming significantly lower power and area.

[1]  Jooheung Lee,et al.  Efficient VLSI architecture for video transcoding , 2009, IEEE Transactions on Consumer Electronics.

[2]  Chin-Feng Tsai,et al.  Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor , 2010, J. Signal Process. Syst..

[3]  Henry Hoffmann,et al.  Evaluation of the Raw microprocessor: an exposed-wire-delay architecture for ILP and streams , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[4]  Stamatis Vassiliadis,et al.  DCT and IDCT Implementations on Different FPGA Technologies , 2022 .

[5]  Dimitrios Hatzinakos,et al.  Multiresolution digital watermarking: algorithms and implications for multimedia signals , 1999 .

[6]  Martin Margala,et al.  MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor , 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.

[7]  T. Mohsenin,et al.  A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling , 2008, 2008 IEEE Symposium on VLSI Circuits.

[8]  M. Koppen,et al.  Content-based watermarking using image texture , 2002, 6th International Conference on Signal Processing, 2002..

[9]  M.A. Ashour,et al.  Hardware implementation of the encoder modified mid-band exchange coefficient technique (MMBEC) based on FPGA , 2007, 2007 Internatonal Conference on Microelectronics.

[10]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[11]  André DeHon,et al.  MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.