Comprehensive, scalable design guidance for serpentine time delay variation in digital system

In digital systems, serpentine routing of lines has been widely used to control timing delay for timing margin management[1-2]. Layout implementation of serpentine routing without careful design consideration may lead to timing violation due to unwanted delay variation[1-4]. This paper discusses the potential design issue of nonideal serpentine line time delay using simulation results correlated with measurements. Two different topology types of serpentine structures implemented in a test board were utilized to determine general performance trends based on key design parameters. Measured data were correlated with results from a commercially available 3D FEM simulation tool and analyzed to generate design guidance as a function of the number of serpentine legs, leg-to-leg gap, leg length, and signal edge rate. This quantitative, scalable design guidance on time delay variation due to serpentine routing can help a designer to avoid potential design risk due to poor serpentine routing design practice.