Novel digital control schemes of dynamic current sharing for multiphase buck converter

High frequency load transient response and dynamic voltage scaling are two most important performance metrics in multiphase voltage regulator design to support high current dynamic loads, such as processor. As load frequency is increased up to MHz range or the regulator is enforced to run in boost operation mode during dynamic voltage downward transition, the voltage regulator suffers from imbalanced phase current which can introduce extra power loss and electrical stress on power components thus degrade the reliability of the overall system. In this paper, positive current sharing during high frequency load transient and negative current sharing during dynamic voltage downward transition are thoroughly studied. Load frequency detection scheme for disabling the nonlinear PWM control loop in high frequency transient is presented, and protection in the loop is proposed to accurate cycle by cycle current limiting scheme to crank the maximum current and mitigate the beat frequency oscillation are proposed. Critical design parameters in MOSFET driver IC design and adaptive voltage positioning (AVP) loop bandwidth are optimized. Dynamic power loss is reduced due to suppressed circulating current among phases. Experiment results are provided as verification of the analyses and solutions.