Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.

[1]  C. Duvvury.  ESD qualification changes for 45nm and beyond , 2008, 2008 IEEE International Electron Devices Meeting.

[2]  Jon Barth,et al.  TLP calibration, correlation, standards, and new techniques , 2001 .

[3]  E. Rosenbaum,et al.  Gate oxide reliability under ESD-like pulse stress , 2004, IEEE Transactions on Electron Devices.

[4]  Dimitri Linten,et al.  A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS , 2004 .

[5]  Lining Zhang,et al.  Investigation of LOCOS- and Polysilicon-Bound Diodes for Robust Electrostatic Discharge (ESD) Applications , 2010, IEEE Transactions on Electron Devices.

[6]  Junjun Li,et al.  Degradation of High-$k$/Metal Gate nMOSFETs Under ESD-Like Stress in a 32-nm Technology , 2011, IEEE Transactions on Device and Materials Reliability.

[7]  Chun-Yu Lin,et al.  ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process , 2012, IEEE Transactions on Microwave Theory and Techniques.

[8]  M. Ker.  Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI , 1999 .

[9]  C. Duvvury,et al.  Latch-up in 65nm CMOS technology: a scaling perspective , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[10]  Ming-Dou Ker,et al.  ESD implantations for on-chip ESD protection with layout consideration in 0.18-/spl mu/m salicided CMOS technology , 2005 .

[11]  Ming-Dou Ker,et al.  Component-Level Measurement for Transient-Induced Latch-up in CMOS ICs Under System-Level ESD Considerations , 2006, IEEE Transactions on Device and Materials Reliability.

[12]  Chun-Yu Lin,et al.  Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High- $k$ /Metal Gate CMOS Process , 2015, IEEE Transactions on Electron Devices.

[13]  Yan Han,et al.  Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications , 2008 .