Barrier Properties of ALD W 1 . 5 N Thin Films

W1.5N films grown by ALD from WF6, NH3, C2H4 and SiH4 as precursors were tested as Cu diffusion barriers in p/n diodes and capacitors with SiO2 as a dielectric. I-V and C-V, C-t characteristics were measured before and after anneal. The layers exhibit excellent barrier properties against both Cu and Al interaction with silicon. No changes of current and capacitance attributed to a barrier failure were observed after annealing at 400 C. Samples without the barrier showed a drastic change of the I-V characteristics. The composition of the films was W1.5N as determined with RBS, being a mixture of WN and W2N phases The RMSroughness was as low as 0.5-0.7 nm for a film with a thickness of 25 nm. INTRODUCTION Continuous scaling of Cu interconnect features requires very thin and conformal barriers against the diffusion of Cu into dielectrics and silicon. For this purpose Atomic Layer Deposition (ALD) is superior to PVD and CVD. Tungsten nitride is a possible candidate as a diffusion barrier. ALD using WF6 and NH3 as precursors was reported to produce films with resistivities as high as ~ 4500 μΩcm [1, 2]. For the first time we present ALD tungsten nitride layers with a resistivity as low as 480 μΩcm [3]. This improvement is ascribed to the additional use of C2H4 and SiH4 in the deposition process. EXPERIMENTAL The diffusion properties were evaluated on p/n diodes and capacitors with 200 nm of wet thermal oxides grown in water vapor. Diodes and capacitors were made on separate 100 nm Figure 1. Diodes with varying active area D1÷D5 (100x100 ÷ 1600x1600 μm) and different geometry of the contacts openings DL1÷3, DS1÷3 and constant active area (1600x1600 μm). (100) n-type Si substrates. This is done to avoid the capacitor to become contaminated during diode test. Diodes with an area varying between (100 μm) and (1600 μm) had a different geometry of the contacts openings and a varying perimeter to area ratio (see figure 1). A 0.25 micron deep p/n junction was fabricated with BF2 ion implantation. Diodes were tested with a barrier thickness of 7 or 10 nm, capacitors with 10 nm. Cu reference diodes were made with an ultra thin (~3 nm) adhesion layer of W1.5CN. Cu reference capacitors were made with a direct Cu contact to SiO2. Cu or Al was used as a metal for electrodes. Both as prepared and annealed devices were measured to monitor Cu-diffusion. Annealing was done at 200 and 400 oC in N2/ 5% H2 ambient for 30 min. C-V tests of diodes were done under reverse bias. I-V measurements were performed using a HP 4256A parameter analyser and the Material Development Corporations (MDC) CSMWin program. The leakage current is measured at –5 V. Leakage of the set up was 5x10 A. C-V and C-t tests of capacitors were done at 10 kHz with a HP 4140B pA meter as a DC voltage source, a HP 4275 multifrequency meter and the MDC CSMWin computer program. RESULTS AND DISCUSSION