Digital intermediate-frequency dynamic range expansion method

The invention provides a digital intermediate-frequency dynamic range expansion method. A significance bit detection unit, a data left shift unit and an output data gain adjusting unit are included. The method comprises the following steps of sending a group of integer ADC sampling data with n-bit resolution into an RAM of a FPGA, and simultaneously carrying out data significance bit detection; when input of the group of the ADC sampling data is completed, acquiring a maximum significant bit digit and taking as a M; sending a difference of n-M into an operation streamline of the FPGA and successively carrying out left shift n-M bit on each ADC data in the data left shift unit; sending the data after left shift into an intermediate-frequency digital signal processing unit, in the intermediate-frequency digital signal processing unit, intercepting output data of all the integer data multiplication operations, except for a last level of multiplication operation; converting a data format of the output data of the intermediate-frequency digital signal processing unit from the integer into a floating point type; for floating point type output data, according to a left shift digit n-M in a data left shift unit, carrying out gain adjusting.