Automated System-Level Test Development for Mixed-Signal Circuits

While in the digital domain, test development is primarily conducted with the use of automated tools, knowledge-based, ad hoc test methods have been in use in the analog domain. High levels of design integration and increasing complexity of analog blocks within a system necessitate automated system-level analog test development tools. We outline a methodology for specification-based automated test generation and fault simulation for analog circuits. Test generation is targeted at providing the highest coverage for each specified parameter. The flexibility of assigning analog test attributes is utilized for merging tests leading to test time reduction with no loss in test coverage. Further optimization in test time is obtained through fault simulations by selecting tests that provide adequate coverage in terms of several components and dropping the ones that do not provide additional coverage. A system-level test set target in the given set of specifications, along with fault and yield coverages in terms of each targeted parameter, and testability problems are determined through the proposed methodology.

[1]  M. J. Ohletz L/sup 2/RFM-local layout realistic faults mapping scheme for analogue integrated circuits , 1996, Proceedings of Custom Integrated Circuits Conference.

[2]  Kwang-Ting Cheng,et al.  Test generation for linear time-invariant analog circuits , 1999 .

[3]  Abhijit Chatterjee,et al.  Efficient test generation for transient testing of analog circuits using partial numerical simulation , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[4]  Bozena Kaminska,et al.  Analog circuit testing based on sensitivity computation and new circuit modeling , 1993, Proceedings of IEEE International Test Conference - (ITC).

[5]  Bozena Kaminska,et al.  Parametric fault simulation and test vector generation , 2000, DATE '00.

[6]  Jacob A. Abraham,et al.  Analog Testing with Time Response Parameters , 1996, IEEE Des. Test Comput..

[7]  Alberto L. Sangiovanni-Vincentelli,et al.  Minimizing production test time to detect faults in analog circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Ronald S. Gyurcsik,et al.  Optimal ordering of analog integrated circuit tests to minimize test time , 1991, 28th ACM/IEEE Design Automation Conference.

[9]  Ronald L. Rivest,et al.  Introduction to Algorithms , 1990 .

[10]  L. S. Milor,et al.  A tutorial introduction to research on analog and mixed-signal circuit testing , 1998 .

[11]  Kwang-Ting Cheng,et al.  Pseudorandom testing for mixed-signal circuits , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Pierre Duhamel,et al.  Automatic test generation techniques for analog circuits and systems: A review , 1979 .

[13]  Clifford Stein,et al.  Introduction to Algorithms, 2nd edition. , 2001 .

[14]  Bozena Kaminska,et al.  FaultMaxx: A Perturbation Based Fault Modeling and Simulation for Mixed-Signal Circuits , 2001 .

[15]  F. Joel Ferguson,et al.  Carafe: an inductive fault analysis tool for CMOS VLSI circuits , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.