Integrated-circuit reliability simulation including dynamic stress effects

The development of high-reliability integrated circuits requires accurate prediction of circuit lifetime including dynamic stress effects. A systematic approach for classifying dynamic stress conditions and accounting for AC-induced excessive hot-carrier damage using an effective degradation factor is described. An equivalent DC degradation monitor is simulated using a two-pass approach. Experimental results on digital circuits, including memory circuits, are presented. In particular, results are presented on substrate currents in NAND gates, degradation in precharging current, and a SRAM cell and peripheral circuits.<<ETX>>

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