An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors

Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAM seems to be the most promising alternative. With high density and negligible leakage power, STT-RAMs open a new door to respond to future demands of multi-core systems, i.e., large on-chip caches. However, several problems in STT-RAMs should be overcome to make it applicable in on-chip caches. High probability of write error due to stochastic switching is a major problem in STT-RAMs. Conventional Error-Correcting Codes (ECCs) impose significant area and energy consumption overheads to protect STT-RAM caches. These overheads in multi-core processors with large last-level caches are not affordable. In this paper, we propose Asymmetry-Aware Protection Technique (A<inline-formula><tex-math notation="LaTeX">$^2$</tex-math><alternatives> <inline-graphic xlink:href="azad-ieq1-2628742.gif"/></alternatives></inline-formula>PT) to efficiently protect the STT-RAM caches. A<inline-formula><tex-math notation="LaTeX">$^2$</tex-math><alternatives> <inline-graphic xlink:href="azad-ieq2-2628742.gif"/></alternatives></inline-formula>PT benefits from error rate asymmetry of STT-RAM write operations to provide the required level of cache protection with significantly lower overheads. Compared with the conventional ECC configuration, the evaluation results show that A<inline-formula> <tex-math notation="LaTeX">$^2$</tex-math><alternatives><inline-graphic xlink:href="azad-ieq3-2628742.gif"/> </alternatives></inline-formula>PT reduces the area and energy consumption overheads by about 42 and 50 percent, respectively, while providing the same level of protection. Moreover, A<inline-formula><tex-math notation="LaTeX">$^2$ </tex-math><alternatives><inline-graphic xlink:href="azad-ieq4-2628742.gif"/></alternatives></inline-formula>PT decreases the number of bit switching in write operations by 28 percent, which leads to about 25 percent saving in write energy consumption.

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