Global wires: harmful?

In this paper a shift is proposed in the design of vlsi circuits. In conventional design higher levels of synthesis have to deliver a gate and net list, from which layout synthesis has to built a mask specification for manufacturing. Analysis, mainly timing analysis, is built in a feedback loop to catch violations of timing requirements before sign-off. These violations are used to hand an updated specification to synthesis. Such iteration is not desirable, and for really high performance not feasible. To come to a design flow, higher level synthesis should distribute delay over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays.

[1]  S. Wolf,et al.  Silicon Processing for the VLSI Era , 1986 .

[2]  Joel Grodstein,et al.  A delay model for logic synthesis of continuously-sized networks , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[3]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[4]  S. Akiyama,et al.  Multilayer CMOS device fabricated on laser recrystallized silicon islands , 1983, 1983 International Electron Devices Meeting.

[5]  Niklaus Wirth,et al.  Program development by step-wise refinement , 1971 .

[6]  David R. Kaeli,et al.  VLSI design in the 3rd dimension , 1998, Integr..

[7]  Narendra V. Shenoy,et al.  Embedded tutorial: Speed - new paradigms in design for performance , 1996, ICCAD.

[8]  Ivan E. Sutherland,et al.  Logical effort: designing for speed on the back of an envelope , 1991 .

[9]  Niklaus Wirth,et al.  Program development by stepwise refinement , 1971, CACM.

[10]  N. P. van der Meijs,et al.  Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[11]  Mary Shaw,et al.  Global variable considered harmful , 1973, SIGP.

[12]  Robert K. Brayton,et al.  Delay-optimal technology mapping by DAG covering , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).