Improvement of Endurance and Data-retention in 40nm TaOX-based ReRAM by Finalize Verify

This paper investigates Set/Reset endurance cycles utilizing Verify operation in order to extend the acceptable dataretention time of 40nm TaOX based Resistive Random Access Memory (ReRAM). Applying Verify operation enhances dataretention time drastically at low Set/Reset cycles. However, as Set/Reset cycles with applying Verify operation increase, ReRAM-cell deteriorates and bit-error rate (BER) of low resistance state (LRS) increases [1]. To suppress this deterioration by Verify-stress, “Finalize_Verify” is proposed. As a result, the data-retention time of LRS is enhanced even at the high Set/Reset cycles. In addition, assuming to using errorcorrecting code (ECC), effect of ECC strength in Verify operation and Finalize_Verify operation is investigated.

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