The implementation of 100MHz data acquisition based on FPGA

A high-speed data acquisition based on FPGA and implemented in VHDL is presented in this paper. According to the requirement of a new radar system, several new technologies are adopted in the design and implementation such as time compression storage and memory rewriting. As a result, the system performs well with low dissipation of power, simple circuit layout and high efficient utilization of memory. The acquisition system comprises four parts: ADC circuit, data package and interface, sampling data memory and data flag memory. To implement large circuit, FPGA is adopted in this data acquisition system with reconfigurable ability and constant delay feature according to Z.G. Vranesic (1999).