Digitally adjustable resistors in CMOS for high-performance applications

Methods by which CMOS circuits can be adjusted digitally to generate controlled impedances for use in high-performance circuits are described. Since digital signals are the only inputs to these circuits, on-chip DC power dissipation can be reduced, the circuit can be made more robust, and the impedance of the circuit can be adjusted by manipulating the input digital information. A design of a CMOS series terminated line driver is discussed, and the utilization of the controlled impedance in terminating transmission lines on-chip, constant delay lines, and controlled di/dt output buffers is discussed. >

[1]  T. J. Gabara,et al.  Improved DC matching of CMOS circuits using Rotational Symmetry , 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

[2]  A. Maury,et al.  A high performance submicron CMOS process with self-aligned chan-stop and punch-through implants (Twin-Tub V) , 1986, 1986 International Electron Devices Meeting.

[3]  T. F. Knight,et al.  A self-terminating low-voltage swing CMOS output driver , 1988 .

[4]  M. Banu.  100khz - 1ghz Nmos Variable-frequency Oscillator With Analog And Digital Control , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[5]  T. J. Gabara.  Reduced ground bounce and improved latch-up suppression through substrate conduction , 1988 .

[6]  T. J. Gabara,et al.  A 200 MHz 100 K ECL output buffer for CMOS ASICs , 1990, Third Annual IEEE Proceedings on ASIC Seminar and Exhibit.

[7]  T. Gabara,et al.  Ground Bounce Control In Cmos Integrated Circuits , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[8]  D.A. Hodges,et al.  All-MOS charge-redistribution analog-to-digital conversion techniques. II , 1975, IEEE Journal of Solid-State Circuits.